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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: ACEu1furYA2yvt527K2Q6cn3RhPekJOewn6hSw6cIcGWl3sB+unxHEZAhquS8u/AVndHcHtjK7uBZJ47NuFiBGt/R+RGpoYogF+MubWZ8YuPsaOrNUgDyXTnQfw5hHw2bWeMifPfcPc24Vys5e7Unu09Eb//WCclD7itQYx7XBA7SG/RH1OpIbxsHonKf9B/3wIFnW7ZzUF+GmfqPmPEYFe/YJY0TZxqnM9kd08D+3425Pqswm05uxyh2+EfNNLD9GRKHRj9XiGl4LNJ+sZyvcEtLYh/b+5JMf37I9cEO2VsSPJqzdi7CnaqLRB8IFx/oqEFEsr/TFSBmj2RRz30oyuuNjw69VVj20XhFcvh96na/nN+2WSwMxMjyu1Dsp+3CHLtuNzVII2mt5i8eICxBjlTxCIzztY8NB7jvnH6nE/I60NBvhOGFcP+xuwFSfS8wnA9YroMyn1f8mx31bp4I3F3cFMGn8ewyq0t99m1/Fh8FgTByFol++blKLG1zhSUGnUkJ9GqKl/V+6SSeozcvl5tZ4PZPzZrSnYUegvp9I1zEOLJVEgIipOYtlB1Y/fQgon+PepAVE3NwIPUeGFJ2GT63xt+MjDJtbHVoa36zDiCX6BF3ofIpJPJ8MTq26AXd3o9eef1ndHhZ/WiIyFagO069F96X9HKOeP2vDE4x8KEIZa3ANqnUEaSrne7ns2rI/6Cb4NbMXffQSaVFp0V/z2Pc59LRXn6x9O4wgANKsiXQEf9J0vy6sOq6T8Kb29ISKVpt5oHgvEHWEAPYE0z2cdpi+/gbZB1G6t9/p84gLINsstbdkNzQk5ktuYvOJq4Q9K/MUGKHqQiTAfurTp9wYOQRAoacUj3mHk+0mzmt98IXEwmmQwwX7aI4aplvPEqYnB/6cmowWbLwzjAmU5iOBmnMh+wkGLgrTTnNyR5yOrc9fQ4D5Sx6GQwlr7RkXkV8leGnZ4+zJT8FNcY4XczRkrLuT0pHbSvmQ7CEPTl7uy2b5ZdmiMUoDbqpJM6aFPX34k+cVqzDrYdHp0RxIqxbymOUFQE2sW1LGYDbU4rHYt3KczXzVuMR+YjgwSO7XweGzRwyrbqdKqNahklu16tBJ5luo8KsnDZ1Vs8eXnLzlfGGMc8CE92FSw/1trL2eSCkbqgTbDWm8Gln+/tvU7nlsSeXaWObm5YXqUYvo4/G2hqV1H2SXyr8OCzItswzepVPKuOpOoSSUDWYwdxvsjvW5JPNz9IVOtkJo5+xzWpChwDxTo5+1xl0voH/T7zket/Ppk/juv1hUkHsoC2By1xSfQHrIpszqFAXT2lqG9sGHa9vxoc3ljK5wza3zBqhQtXLWwf7/oGSnb8IJYedoCroLSBDBqK3iThcasRkw0SQTIDVNZuUj1nOWJx2dCG6+1t35jT80J9NMNjz0uyaseTwOaH4GeqNI2Wkxz2YKe81A7QwEgcCqCRuZ7hekSzsVXrTAiM+vKWYU7YLVBulnFy06DrbpUQjhQWwY2p2th2RqTDoaS1yALspEHdKKrOGgYJi2oV4jy/3j7zWEuPI03DTKvLadr+IL3noUQxkX+UHX25ZR+xtEcoozMIch8kw21T X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5486c598-e209-49a1-103e-08dc1e0162f6 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Jan 2024 23:57:28.4817 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: cCHqHOUHdJJfOnjEru2d5ENOJnysoWe0cCOPQRUrZawtowOgV7NbKTXtUcrdp5aj X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7038 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240125_155745_624035_17F48016 X-CRM114-Status: GOOD ( 16.18 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This was needed because the STE code required the STE to be in ABORT/BYPASS inorder to program a cdtable or S2 STE. Now that the STE code can automatically handle all transitions we can remove this step from the attach_dev flow. A few small bugs exist because of this: 1) If the core code does BLOCKED -> UNMANAGED with disable_bypass=false then there will be a moment where the STE points at BYPASS. Since this can be done by VFIO/IOMMUFD it is a small security race. 2) If the core code does IDENTITY -> DMA then any IOMMU_RESV_DIRECT regions will temporarily become BLOCKED. We'd like drivers to work in a way that allows IOMMU_RESV_DIRECT to be continuously functional during these transitions. Make arm_smmu_release_device() put the STE back to the correct ABORT/BYPASS setting. Fix a bug where a IOMMU_RESV_DIRECT was ignored on this path. As noted before the reordering of the linked list/STE/CD changes is OK against concurrent arm_smmu_share_asid() because of the arm_smmu_asid_lock. Tested-by: Shameer Kolothum Tested-by: Nicolin Chen Tested-by: Moritz Fischer Reviewed-by: Nicolin Chen Signed-off-by: Jason Gunthorpe --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index cf3e348cb9abe1..bf5698643afc50 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2535,7 +2535,6 @@ static void arm_smmu_disable_pasid(struct arm_smmu_master *master) static void arm_smmu_detach_dev(struct arm_smmu_master *master) { unsigned long flags; - struct arm_smmu_ste target; struct arm_smmu_domain *smmu_domain = master->domain; if (!smmu_domain) @@ -2549,11 +2548,6 @@ static void arm_smmu_detach_dev(struct arm_smmu_master *master) master->domain = NULL; master->ats_enabled = false; - if (disable_bypass) - arm_smmu_make_abort_ste(&target); - else - arm_smmu_make_bypass_ste(&target); - arm_smmu_install_ste_for_dev(master, &target); /* * Clearing the CD entry isn't strictly required to detach the domain * since the table is uninstalled anyway, but it helps avoid confusion @@ -2901,9 +2895,18 @@ static struct iommu_device *arm_smmu_probe_device(struct device *dev) static void arm_smmu_release_device(struct device *dev) { struct arm_smmu_master *master = dev_iommu_priv_get(dev); + struct arm_smmu_ste target; if (WARN_ON(arm_smmu_master_sva_enabled(master))) iopf_queue_remove_device(master->smmu->evtq.iopf, dev); + + /* Put the STE back to what arm_smmu_init_strtab() sets */ + if (disable_bypass && !dev->iommu->require_direct) + arm_smmu_make_abort_ste(&target); + else + arm_smmu_make_bypass_ste(&target); + arm_smmu_install_ste_for_dev(master, &target); + arm_smmu_detach_dev(master); arm_smmu_disable_pasid(master); arm_smmu_remove_master(master);