diff mbox

[v6,2/2] dt-bindings: document Rockchip saradc

Message ID 8132020.MqcOnlblHg@diego (mailing list archive)
State New, archived
Headers show

Commit Message

Heiko Stuebner July 23, 2014, 9:24 p.m. UTC 
This add the necessary binding documentation for the saradc found in all recent
processors from Rockchip.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
changes since v5:
- remove clock-frquency property as described in patch 1/2

 .../bindings/iio/adc/rockchip-saradc.txt           | 24 ++++++++++++++++++++++
 1 file changed, 24 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt

Comments

Jonathan Cameron Aug. 7, 2014, 2:15 p.m. UTC | #1 
On 23/07/14 22:24, Heiko Stübner wrote:
> This add the necessary binding documentation for the saradc found in all recent
> processors from Rockchip.
> 
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Applied to the togreg branch of iio.git.
I have exercised a small amount of discretion wrt to the standard 3 weeks
as there really is very little different in here from previous versions
and no one has raised any comments on them.

It's nearly 3 weeks anyway!

J
> ---
> changes since v5:
> - remove clock-frquency property as described in patch 1/2
> 
>  .../bindings/iio/adc/rockchip-saradc.txt           | 24 ++++++++++++++++++++++
>  1 file changed, 24 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
> 
> diff --git a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
> new file mode 100644
> index 0000000..5d3ec1d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
> @@ -0,0 +1,24 @@
> +Rockchip Successive Approximation Register (SAR) A/D Converter bindings
> +
> +Required properties:
> +- compatible: Should be "rockchip,saradc"
> +- reg: physical base address of the controller and length of memory mapped
> +       region.
> +- interrupts: The interrupt number to the cpu. The interrupt specifier format
> +              depends on the interrupt controller.
> +- clocks: Must contain an entry for each entry in clock-names.
> +- clock-names: Shall be "saradc" for the converter-clock, and "apb_pclk" for
> +               the peripheral clock.
> +- vref-supply: The regulator supply ADC reference voltage.
> +- #io-channel-cells: Should be 1, see ../iio-bindings.txt
> +
> +Example:
> +	saradc: saradc@2006c000 {
> +		compatible = "rockchip,saradc";
> +		reg = <0x2006c000 0x100>;
> +		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
> +		clock-names = "saradc", "apb_pclk";
> +		#io-channel-cells = <1>;
> +		vref-supply = <&vcc18>;
> +	};
>
Heiko Stuebner Aug. 30, 2014, 12:41 p.m. UTC | #2 
Am Donnerstag, 7. August 2014, 15:15:52 schrieb Jonathan Cameron:
> On 23/07/14 22:24, Heiko Stübner wrote:
> > This add the necessary binding documentation for the saradc found in all
> > recent processors from Rockchip.
> > 
> > Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> 
> Applied to the togreg branch of iio.git.
> I have exercised a small amount of discretion wrt to the standard 3 weeks
> as there really is very little different in here from previous versions
> and no one has raised any comments on them.

Did the binding patch make it into any tree? Because when I grep for saradc in 
either linux-next or the iio tree I only get patch 1/2 (the driver itself) but 
the binding document is somehow missing.


Thanks
Heiko


> 
> It's nearly 3 weeks anyway!
> 
> J
> 
> > ---
> > changes since v5:
> > - remove clock-frquency property as described in patch 1/2
> > 
> >  .../bindings/iio/adc/rockchip-saradc.txt           | 24
> >  ++++++++++++++++++++++ 1 file changed, 24 insertions(+)
> >  create mode 100644
> >  Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt> 
> > diff --git a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
> > b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt new file
> > mode 100644
> > index 0000000..5d3ec1d
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
> > @@ -0,0 +1,24 @@
> > +Rockchip Successive Approximation Register (SAR) A/D Converter bindings
> > +
> > +Required properties:
> > +- compatible: Should be "rockchip,saradc"
> > +- reg: physical base address of the controller and length of memory
> > mapped
> > +       region.
> > +- interrupts: The interrupt number to the cpu. The interrupt specifier
> > format +              depends on the interrupt controller.
> > +- clocks: Must contain an entry for each entry in clock-names.
> > +- clock-names: Shall be "saradc" for the converter-clock, and "apb_pclk"
> > for +               the peripheral clock.
> > +- vref-supply: The regulator supply ADC reference voltage.
> > +- #io-channel-cells: Should be 1, see ../iio-bindings.txt
> > +
> > +Example:
> > +	saradc: saradc@2006c000 {
> > +		compatible = "rockchip,saradc";
> > +		reg = <0x2006c000 0x100>;
> > +		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
> > +		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
> > +		clock-names = "saradc", "apb_pclk";
> > +		#io-channel-cells = <1>;
> > +		vref-supply = <&vcc18>;
> > +	};
Jonathan Cameron Aug. 30, 2014, 8:08 p.m. UTC | #3 
On 30/08/14 13:41, Heiko Stübner wrote:
> Am Donnerstag, 7. August 2014, 15:15:52 schrieb Jonathan Cameron:
>> On 23/07/14 22:24, Heiko Stübner wrote:
>>> This add the necessary binding documentation for the saradc found in all
>>> recent processors from Rockchip.
>>>
>>> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
>>
>> Applied to the togreg branch of iio.git.
>> I have exercised a small amount of discretion wrt to the standard 3 weeks
>> as there really is very little different in here from previous versions
>> and no one has raised any comments on them.
> 
> Did the binding patch make it into any tree? Because when I grep for saradc in 
> either linux-next or the iio tree I only get patch 1/2 (the driver itself) but 
> the binding document is somehow missing.
Good spot.  Interestingly I had the file in my local tree but not the commit.
Odd, but now applied to the togreg branch of iio.git and pushed out.

Sorry about that!

Jonathan
> 
> 
> Thanks
> Heiko
> 
> 
>>
>> It's nearly 3 weeks anyway!
>>
>> J
>>
>>> ---
>>> changes since v5:
>>> - remove clock-frquency property as described in patch 1/2
>>>
>>>  .../bindings/iio/adc/rockchip-saradc.txt           | 24
>>>  ++++++++++++++++++++++ 1 file changed, 24 insertions(+)
>>>  create mode 100644
>>>  Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt> 
>>> diff --git a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
>>> b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt new file
>>> mode 100644
>>> index 0000000..5d3ec1d
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
>>> @@ -0,0 +1,24 @@
>>> +Rockchip Successive Approximation Register (SAR) A/D Converter bindings
>>> +
>>> +Required properties:
>>> +- compatible: Should be "rockchip,saradc"
>>> +- reg: physical base address of the controller and length of memory
>>> mapped
>>> +       region.
>>> +- interrupts: The interrupt number to the cpu. The interrupt specifier
>>> format +              depends on the interrupt controller.
>>> +- clocks: Must contain an entry for each entry in clock-names.
>>> +- clock-names: Shall be "saradc" for the converter-clock, and "apb_pclk"
>>> for +               the peripheral clock.
>>> +- vref-supply: The regulator supply ADC reference voltage.
>>> +- #io-channel-cells: Should be 1, see ../iio-bindings.txt
>>> +
>>> +Example:
>>> +	saradc: saradc@2006c000 {
>>> +		compatible = "rockchip,saradc";
>>> +		reg = <0x2006c000 0x100>;
>>> +		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
>>> +		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
>>> +		clock-names = "saradc", "apb_pclk";
>>> +		#io-channel-cells = <1>;
>>> +		vref-supply = <&vcc18>;
>>> +	};
> 
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diff mbox

Patch

diff --git a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
new file mode 100644
index 0000000..5d3ec1d
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
@@ -0,0 +1,24 @@ 
+Rockchip Successive Approximation Register (SAR) A/D Converter bindings
+
+Required properties:
+- compatible: Should be "rockchip,saradc"
+- reg: physical base address of the controller and length of memory mapped
+       region.
+- interrupts: The interrupt number to the cpu. The interrupt specifier format
+              depends on the interrupt controller.
+- clocks: Must contain an entry for each entry in clock-names.
+- clock-names: Shall be "saradc" for the converter-clock, and "apb_pclk" for
+               the peripheral clock.
+- vref-supply: The regulator supply ADC reference voltage.
+- #io-channel-cells: Should be 1, see ../iio-bindings.txt
+
+Example:
+	saradc: saradc@2006c000 {
+		compatible = "rockchip,saradc";
+		reg = <0x2006c000 0x100>;
+		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
+		clock-names = "saradc", "apb_pclk";
+		#io-channel-cells = <1>;
+		vref-supply = <&vcc18>;
+	};