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Mon, 29 Apr 2024 21:44:06 -0700 From: Nicolin Chen To: , CC: , , , , , , , , Subject: [PATCH v6 2/6] iommu/arm-smmu-v3: Add CS_NONE quirk Date: Mon, 29 Apr 2024 21:43:45 -0700 Message-ID: <81d79f51c69604a38ea4f72c8ac2c573c52e8609.1714451595.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB52:EE_|DM4PR12MB6566:EE_ X-MS-Office365-Filtering-Correlation-Id: 70bae28c-ecc0-41da-730c-08dc68d02f14 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|1800799015|376005|36860700004|82310400014; X-Microsoft-Antispam-Message-Info: AYcFc4NQhCc2V7dyelOnH3moc8d46NG2E0pi/UEW61LSl47+QMY7h1tvHXhA56NZu8yhWLydOujuHdgiH6wzEXUX5v5WfxjysXGSsHE7OJ+yTLEfv8xuVx8nU7pRXLcY8AqE5gFcw7ts2pSL1FgwFOndFWuDlUa36kTxa5phBdPE7XsZCPLJpggQp/0104ilWUV1Xznh9LQ/927kgI/BC58Z0ej+GgIPoG6KR96RR6sa7rQfYAldu8HaYxqlED5RlS2GorJD7qnHy4qEg1Im0YYPPoMWj/X1rr2m81xvy2GupCw3C50c8FwiXxCZJax0/Y/WEV5qlB1mo0Ah4RiWNQ15UPxP4nMmySnlbNoffSEuaa3pfih/XcU2Xj7KJLTSzlTD5C8q0EzxJ4hOkci/JngNrRJ13OKIu0htWb2D77CrYRBvTx1z8C+czquKfTgNELQ5rrBYQrqhWyCScmAtrVoucvrcp1m1RVhmrAEyYPhNZOC/8cZCUoXlIcOo2qJA8mCUe7+FcvFVNUy9iISmvm0lxHYSUs06C58glUo9sOAuAUCN9lYewwC7Ze41zvOF9LOkHkbZN+MN61rJkf47SPKmTREVi6udH3Vv17Nb8z3Rb3v7V4iZSOK0VZtiiQpKEsNpRbExiqV25KCUvqQDgmF/WK7oBluJbfHB4wPBpM1h9fFE9URwWZdiW/HE4IccqNSAiJrRt8rBRKFudGcViFkLB9gGqTikd845scfgpdYSW9aoS8KVN5EocQR7K0l0ixjKCqS6tDGnYXO9Xx9RfWWya/OBQ20/HGCfreDb5L6SWPlX4vqG0f/q6FdktNjH3GGc+B+EbUMWtvOut7O3KYVfmophlvVEv4+BGAaOJiyomcxW3dOWg+cWtjn/NokXXE5yMgGWGJaXco0PtPcCXtD1EFlty/cPbtdpGAmP0D+j0yXAsSBMIgo9rFsRDMYY0rIn4RCfCUlXPn3dGy0jcUV3FTZohKBoNvzulkTrSzzJuJVMBBfr2Hl9+Arj5+uWW4SCdgCh4GNPqFG7eP74GD0SH1dnuqaalQCy2ogL/gvaO9m1tlG5tG1ZyM7E2+y98fPFvlMowxGD/mhMqoWFH4GJZL2LOjeP4XBKRdm7kvhZzTtdfim6C9waXZCBfn5sQDOFgDTcxDwFyhtzXLAEHWH1UQpIkG5mtvIphwe5wGf3J6Bqp8Yq53LgsB3uMH1qOlvQx9v/L8v1ipZW/kJlpkGMTisyep+3ovZxmPvjTAB1VOD/i1ZEWB/NHH2tnDG0maagycI/KUq1Q2cFHblNzTCXbNxRk/GYhbod3WWjbrRR5EYlSuaGL4JnA2W7F31s7UDBg2CNj0VttfVJ8JrZ6s5wgbFQf1QGVsRcbhi1r1RBfzKJGfO4pcFkd/Df5k3T X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230031)(1800799015)(376005)(36860700004)(82310400014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Apr 2024 04:44:13.0092 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 70bae28c-ecc0-41da-730c-08dc68d02f14 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB52.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6566 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240429_214423_561614_22BD3CD5 X-CRM114-Status: GOOD ( 14.63 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The CMDQV extension in NVIDIA Tegra241 SoC only supports CS_NONE in the CS field of CMD_SYNC. Add a quirk flag to accommodate that. Signed-off-by: Nicolin Chen Reviewed-by: Jason Gunthorpe --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 10 ++++++++-- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 4 ++++ 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 6a7e6b1ba5f7..b3d03ca01adc 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -334,7 +334,9 @@ static int arm_smmu_cmdq_build_cmd(u64 *cmd, struct arm_smmu_cmdq_ent *ent) cmd[1] |= FIELD_PREP(CMDQ_RESUME_1_STAG, ent->resume.stag); break; case CMDQ_OP_CMD_SYNC: - if (ent->sync.msiaddr) { + if (ent->sync.cs_none) { + cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_NONE); + } else if (ent->sync.msiaddr) { cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_IRQ); cmd[1] |= ent->sync.msiaddr & CMDQ_SYNC_1_MSIADDR_MASK; } else { @@ -371,6 +373,9 @@ static void arm_smmu_cmdq_build_sync_cmd(u64 *cmd, struct arm_smmu_device *smmu, q->ent_dwords * 8; } + if (q->quirks & CMDQ_QUIRK_SYNC_CS_NONE_ONLY) + ent.sync.cs_none = true; + arm_smmu_cmdq_build_cmd(cmd, &ent); } @@ -708,7 +713,8 @@ static int arm_smmu_cmdq_poll_until_sync(struct arm_smmu_device *smmu, struct arm_smmu_cmdq *cmdq, struct arm_smmu_ll_queue *llq) { - if (smmu->options & ARM_SMMU_OPT_MSIPOLL) + if (smmu->options & ARM_SMMU_OPT_MSIPOLL && + !(cmdq->q.quirks & CMDQ_QUIRK_SYNC_CS_NONE_ONLY)) return __arm_smmu_cmdq_poll_until_msi(smmu, cmdq, llq); return __arm_smmu_cmdq_poll_until_consumed(smmu, cmdq, llq); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 2a19bb63e5c6..bbee08e82943 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -510,6 +510,7 @@ struct arm_smmu_cmdq_ent { #define CMDQ_OP_CMD_SYNC 0x46 struct { u64 msiaddr; + bool cs_none; } sync; }; }; @@ -542,6 +543,9 @@ struct arm_smmu_queue { u32 __iomem *prod_reg; u32 __iomem *cons_reg; + +#define CMDQ_QUIRK_SYNC_CS_NONE_ONLY BIT(0) /* CMD_SYNC CS field supports CS_NONE only */ + u32 quirks; }; struct arm_smmu_queue_poll {