| Message ID | 82688bbe03ae2d68af838c2bc7fd20491a7d42b1.1716031610.git.lorenzo@kernel.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Introduce PCIe PHY driver for EN7581 SoC | expand |
On 18/05/2024 13:31, Lorenzo Bianconi wrote: > Introduce device-tree binding documentation for Airoha EN7581 PCIe PHY > driver. > > Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > Tested-by: Zhengping Zhang <zhengping.zhang@airoha.com> How the binding was tested? > Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> A nit, subject: drop second/last, redundant "bindings". The "dt-bindings" prefix is already stating that these are bindings. See also: https://elixir.bootlin.com/linux/v6.7-rc8/source/Documentation/devicetree/bindings/submitting-patches.rst#L18 Subject: drop driver. This is for hardware, not drivers. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
> On 18/05/2024 13:31, Lorenzo Bianconi wrote: > > Introduce device-tree binding documentation for Airoha EN7581 PCIe PHY > > driver. > > > > Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > > Tested-by: Zhengping Zhang <zhengping.zhang@airoha.com> > > How the binding was tested? > > > Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> > > A nit, subject: drop second/last, redundant "bindings". The > "dt-bindings" prefix is already stating that these are bindings. > See also: > https://elixir.bootlin.com/linux/v6.7-rc8/source/Documentation/devicetree/bindings/submitting-patches.rst#L18 > > Subject: drop driver. This is for hardware, not drivers. > > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Do I need to repost it or is it ok to address it applying the patches? Regards, Lorenzo > > Best regards, > Krzysztof >
diff --git a/Documentation/devicetree/bindings/phy/airoha,en7581-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/airoha,en7581-pcie-phy.yaml new file mode 100644 index 000000000000..e26c30d17ff0 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/airoha,en7581-pcie-phy.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/airoha,en7581-pcie-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Airoha EN7581 PCI-Express PHY + +maintainers: + - Lorenzo Bianconi <lorenzo@kernel.org> + +description: + The PCIe PHY supports physical layer functionality for PCIe Gen2/Gen3 port. + +properties: + compatible: + const: airoha,en7581-pcie-phy + + reg: + items: + - description: PCIE analog base address + - description: PCIE lane0 base address + - description: PCIE lane1 base address + + reg-names: + items: + - const: csr-2l + - const: pma0 + - const: pma1 + + "#phy-cells": + const: 0 + +required: + - compatible + - reg + - reg-names + - "#phy-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/phy/phy.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + phy@11e80000 { + compatible = "airoha,en7581-pcie-phy"; + #phy-cells = <0>; + reg = <0x0 0x1fa5a000 0x0 0xfff>, + <0x0 0x1fa5b000 0x0 0xfff>, + <0x0 0x1fa5c000 0x0 0xfff>; + reg-names = "csr-2l", "pma0", "pma1"; + }; + };