From patchwork Mon Oct 15 19:48:10 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Cochran X-Patchwork-Id: 1595381 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id 4062EDFB34 for ; Mon, 15 Oct 2012 19:52:04 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TNqfh-0005pv-ON; Mon, 15 Oct 2012 19:49:53 +0000 Received: from mail-we0-f177.google.com ([74.125.82.177]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1TNqes-0005MF-WF for linux-arm-kernel@lists.infradead.org; Mon, 15 Oct 2012 19:49:04 +0000 Received: by mail-we0-f177.google.com with SMTP id u50so3436193wey.36 for ; Mon, 15 Oct 2012 12:49:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :in-reply-to:references; bh=JZNgUSSzcML1wJYZYndqdbEPfu6eZ7masNvjF1/4K1E=; b=AlYYbThv3AaNEhKQgnYYk8cpAhv1y47NuHjO61JJkvZpQC1V6c+eD3k4/LQhNbQ9ly rmnmk8egdvebFQzXyb9ZYmYhUaUV3rMSDXNrejAg4kp5CxSbcX9/zFj+e8WRfKJ8kTju vwF2edU4H3WwH6EFM+SM4flbLS8xal7uhbXhdl7jQG4NaAR0M0BQZya2feT2k9im8A0/ HrJ5llhoYlqCxoIGWgZ0qP6q16nFYNxxZT/tinlHJIiTtjIbaOYkWKwk09pnFr5ViAQt 8ikoOUnaBhUTZkhu+E2LoQQsfea6h3jzAh2XiDw3+/2uv0/qzry8hvnF7ubBZxkAvnE+ hvEQ== Received: by 10.180.100.35 with SMTP id ev3mr26129105wib.7.1350330542584; Mon, 15 Oct 2012 12:49:02 -0700 (PDT) Received: from localhost.localdomain (089144206171.atnat0015.highway.a1.net. [89.144.206.171]) by mx.google.com with ESMTPS id bn7sm17543324wib.8.2012.10.15.12.48.58 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 15 Oct 2012 12:49:00 -0700 (PDT) From: Richard Cochran To: Subject: [PATCH V2 4/7] cpsw: add a common header file for regsiter declarations Date: Mon, 15 Oct 2012 21:48:10 +0200 Message-Id: <8297fe4fba8e511f97c2c4cab2264aedcfb2f488.1350329726.git.richardcochran@gmail.com> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: References: In-Reply-To: References: X-Spam-Note: CRM114 invocation failed X-Spam-Score: -2.7 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [74.125.82.177 listed in list.dnswl.org] 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (richardcochran[at]gmail.com) -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature Cc: Sriramakrishnan A G , Mugunthan V N , David Miller , linux-arm-kernel@lists.infradead.org, Cyril Chemparathy X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Signed-off-by: Richard Cochran --- drivers/net/ethernet/ti/cpsw_reg.h | 81 ++++++++++++++++++++++++++++++++++++ 1 files changed, 81 insertions(+), 0 deletions(-) create mode 100644 drivers/net/ethernet/ti/cpsw_reg.h diff --git a/drivers/net/ethernet/ti/cpsw_reg.h b/drivers/net/ethernet/ti/cpsw_reg.h new file mode 100644 index 0000000..88fb15f --- /dev/null +++ b/drivers/net/ethernet/ti/cpsw_reg.h @@ -0,0 +1,81 @@ +/* + * Common CPSW register declarations + * + * Copyright (C) 2012 Richard Cochran + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#ifndef _TI_CPSW_REG_H_ +#define _TI_CPSW_REG_H_ + +struct cpsw_port { + u32 control; /* Control Register */ + u32 res1; + u32 max_blks; /* Maximum FIFO Blocks */ + u32 blk_cnt; /* FIFO Block Usage Count (Read Only) */ + u32 tx_in_ctl; /* Transmit FIFO Control */ + u32 port_vlan; /* VLAN Register */ + u32 tx_pri_map; /* Tx Header Priority to Switch Pri Map */ + u32 ts_seq_mtype; /* Time Sync Seq ID Offset and Msg Type */ + u32 sa_lo; /* CPGMAC_SL Source Address Low */ + u32 sa_hi; /* CPGMAC_SL Source Address High */ + u32 send_percent; /* Transmit Queue Send Percentages */ + u32 res2; + u32 rx_dscp_pri_map0; /* Rx DSCP Priority to Rx Packet Mapping */ + u32 rx_dscp_pri_map1; /* Rx DSCP Priority to Rx Packet Mapping */ + u32 rx_dscp_pri_map2; /* Rx DSCP Priority to Rx Packet Mapping */ + u32 rx_dscp_pri_map3; /* Rx DSCP Priority to Rx Packet Mapping */ + u32 rx_dscp_pri_map4; /* Rx DSCP Priority to Rx Packet Mapping */ + u32 rx_dscp_pri_map5; /* Rx DSCP Priority to Rx Packet Mapping */ + u32 rx_dscp_pri_map6; /* Rx DSCP Priority to Rx Packet Mapping */ + u32 rx_dscp_pri_map7; /* Rx DSCP Priority to Rx Packet Mapping */ +}; + +/* Bit definitions for the CONTROL register */ +#define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */ +#define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */ +#define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */ +#define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */ +#define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */ +#define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */ +#define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */ +#define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */ +#define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */ +#define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */ +#define TS_BIT8 (1<<8) /* ts_ttl_nonzero? */ +#define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */ +#define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */ +#define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */ +#define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */ +#define TS_RX_EN (1<<0) /* Time Sync Receive Enable */ + +#define CTRL_TS_BITS \ + (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 | TS_BIT8 | \ + TS_ANNEX_D_EN | TS_LTYPE2_EN | TS_LTYPE1_EN) + +#define CTRL_ALL_TS_MASK (CTRL_TS_BITS | TS_TX_EN | TS_RX_EN) +#define CTRL_TX_TS_BITS (CTRL_TS_BITS | TS_TX_EN) +#define CTRL_RX_TS_BITS (CTRL_TS_BITS | TS_RX_EN) + +/* Bit definitions for the TS_SEQ_MTYPE register */ +#define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */ +#define TS_SEQ_ID_OFFSET_MASK (0x3f) +#define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */ +#define TS_MSG_TYPE_EN_MASK (0xffff) + +/* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */ +#define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3)) + +#endif