Message ID | 85263ce8b058e80cea25c6ad6383eb256ce96cc8.1604988979.git.frank@allwinnertech.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | Second step support for A100 | expand |
On Tue, Nov 10, 2020 at 7:24 AM Frank Lee <frank@allwinnertech.com> wrote: > From: Yangtao Li <frank@allwinnertech.com> > > It is found on many allwinner soc that there is a low probability that > the interrupt status cannot be read in sunxi_pinctrl_irq_handler. This > will cause the interrupt status of a gpio bank to always be active on > gic, preventing gic from responding to other spi interrupts correctly. > > So we should call the chained_irq_* each time enter sunxi_pinctrl_irq_handler(). > > Cc: stable@vger.kernel.org > Signed-off-by: Yangtao Li <frank@allwinnertech.com> Patch applied. Yours, Linus Walleij
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index 9d8b59dafa4b..dc8d39ae045b 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -1141,20 +1141,22 @@ static void sunxi_pinctrl_irq_handler(struct irq_desc *desc) WARN_ON(bank == pctl->desc->irq_banks); + chained_irq_enter(chip, desc); + reg = sunxi_irq_status_reg_from_bank(pctl->desc, bank); val = readl(pctl->membase + reg); if (val) { int irqoffset; - chained_irq_enter(chip, desc); for_each_set_bit(irqoffset, &val, IRQ_PER_BANK) { int pin_irq = irq_find_mapping(pctl->domain, bank * IRQ_PER_BANK + irqoffset); generic_handle_irq(pin_irq); } - chained_irq_exit(chip, desc); } + + chained_irq_exit(chip, desc); } static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl,