From patchwork Tue Apr 2 04:19:37 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kuninori Morimoto X-Patchwork-Id: 2374161 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id 35B893FDDA for ; Tue, 2 Apr 2013 04:22:00 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UMshD-0003F7-3V; Tue, 02 Apr 2013 04:19:43 +0000 Received: from mail-pa0-f54.google.com ([209.85.220.54]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UMshA-0003E8-EE for linux-arm-kernel@lists.infradead.org; Tue, 02 Apr 2013 04:19:41 +0000 Received: by mail-pa0-f54.google.com with SMTP id fa11so55341pad.41 for ; Mon, 01 Apr 2013 21:19:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:date:sender:message-id:to:cc:in-reply-to:references:from :subject:mime-version:content-type; bh=OEgGccdxzKB3e4Y20L3rPgMgzaaNk3p5GFld8KNOC7w=; b=iuEdGc9VJsRzMexMi8PE9MeOCohRBF8EL6bu5JMPFnyl3roC7VfyM1ULwHArbpdDYW OaxGQP1S1/Ah7IS9Au3qTaVlUudg8SUX0oB1DP4HAXgDhpGTRocUYDih94lgKW3Rk28Z QbDJ1IcMyQOO8biDYp5qvkVsAd4jDro4L4MJoZYHi4g59usHxMAgx2fhz5oUyIdxErWk 8OhXznOm3qWjCcWQc8VaO+7Ko4buRW/5si60qhsXMzqalmYqssukMtDL22k45dZd0LIW zge3ZLVNGwNKuILx1HWvLB+uVoydul70LAy9YlTqpaPmLaBFc5Y3z4py/aDZD6kdaYyV GSeQ== X-Received: by 10.68.247.72 with SMTP id yc8mr22078527pbc.23.1364876378848; Mon, 01 Apr 2013 21:19:38 -0700 (PDT) Received: from morimoto-Dell-XPS420.gmail.com (49.14.32.202.bf.2iij.net. [202.32.14.49]) by mx.google.com with ESMTPS id rt13sm539080pac.14.2013.04.01.21.19.36 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Mon, 01 Apr 2013 21:19:37 -0700 (PDT) Date: Mon, 01 Apr 2013 21:19:37 -0700 (PDT) Message-ID: <87ppyd5zu2.wl%kuninori.morimoto.gx@renesas.com> To: Paul , Simon , arnd@arndb.de In-Reply-To: <87sj395zvv.wl%kuninori.morimoto.gx@renesas.com> References: <87zjxvewko.wl%kuninori.morimoto.gx@renesas.com> <87fvzb56n3.wl%kuninori.morimoto.gx@renesas.com> <87sj395zvv.wl%kuninori.morimoto.gx@renesas.com> From: Kuninori Morimoto Subject: [PATCH 2/5 v3] ARM: shmobile: r8a7778: add r8a7778_init_irq_extpin() MIME-Version: 1.0 (generated by SEMI 1.14.6 - "Maruoka") X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130402_001940_603369_6FF2A643 X-CRM114-Status: GOOD ( 17.21 ) X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.220.54 listed in list.dnswl.org] 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (kuninori.morimoto.gx[at]gmail.com) -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature Cc: Magnus , Kuninori Morimoto , linux-arm-kernel@lists.infradead.org, linux-sh@vger.kernel.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org This patch adds r8a7778_init_irq_extpin() for IRQ0 - IRQ3. But this patch doesn't enable DT settings on r8a7778.dts, because R8A7778 chip external IRQ depends on IRQ0 - IRQ3 pin encoding which came from platform board implementation. Signed-off-by: Kuninori Morimoto --- v2 -> v3 - no change arch/arm/mach-shmobile/include/mach/r8a7778.h | 1 + arch/arm/mach-shmobile/setup-r8a7778.c | 44 +++++++++++++++++++++++++ 2 files changed, 45 insertions(+) diff --git a/arch/arm/mach-shmobile/include/mach/r8a7778.h b/arch/arm/mach-shmobile/include/mach/r8a7778.h index a755dca..e0c6205 100644 --- a/arch/arm/mach-shmobile/include/mach/r8a7778.h +++ b/arch/arm/mach-shmobile/include/mach/r8a7778.h @@ -24,5 +24,6 @@ extern void r8a7778_init_delay(void); extern void r8a7778_init_irq(void); extern void r8a7778_init_irq_dt(void); extern void r8a7778_clock_init(void); +extern void r8a7778_init_irq_extpin(int irlm); #endif /* __ASM_R8A7778_H__ */ diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c index 57d6b0e..2882305 100644 --- a/arch/arm/mach-shmobile/setup-r8a7778.c +++ b/arch/arm/mach-shmobile/setup-r8a7778.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include #include @@ -110,6 +111,49 @@ void __init r8a7778_add_standard_devices(void) r8a7778_register_tmu(1); } +static struct renesas_intc_irqpin_config irqpin_platform_data = { + .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */ + .sense_bitfield_width = 2, +}; + +static struct resource irqpin_resources[] = { + DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */ + DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */ + DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */ + DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */ + DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */ + DEFINE_RES_IRQ(gic_iid(0x3b)), /* IRQ0 */ + DEFINE_RES_IRQ(gic_iid(0x3c)), /* IRQ1 */ + DEFINE_RES_IRQ(gic_iid(0x3d)), /* IRQ2 */ + DEFINE_RES_IRQ(gic_iid(0x3e)), /* IRQ3 */ +}; + +void __init r8a7778_init_irq_extpin(int irlm) +{ + void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE); + unsigned long tmp; + + if (!icr0) { + pr_warn("r8a7778: unable to setup external irq pin mode\n"); + return; + } + + tmp = ioread32(icr0); + if (irlm) + tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */ + else + tmp &= ~(1 << 23); /* IRL mode - not supported */ + tmp |= (1 << 21); /* LVLMODE = 1 */ + iowrite32(tmp, icr0); + iounmap(icr0); + + if (irlm) + platform_device_register_resndata( + &platform_bus, "renesas_intc_irqpin", -1, + irqpin_resources, ARRAY_SIZE(irqpin_resources), + &irqpin_platform_data, sizeof(irqpin_platform_data)); +} + #define INT2SMSKCR0 0x82288 /* 0xfe782288 */ #define INT2SMSKCR1 0x8228c /* 0xfe78228c */