From patchwork Mon Oct 15 19:48:09 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Cochran X-Patchwork-Id: 1595371 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id 78D8FDFB34 for ; Mon, 15 Oct 2012 19:51:34 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TNqfR-0005h7-Ri; Mon, 15 Oct 2012 19:49:38 +0000 Received: from mail-wg0-f49.google.com ([74.125.82.49]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1TNqep-0005S1-R1 for linux-arm-kernel@lists.infradead.org; Mon, 15 Oct 2012 19:49:01 +0000 Received: by mail-wg0-f49.google.com with SMTP id gg4so3239556wgb.18 for ; Mon, 15 Oct 2012 12:48:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :in-reply-to:references; bh=KyUCDv6TUOKfZK6QJJ60JIW7D0igrncNnLvBl8fMIVc=; b=HLyofshZBit3YXIQW3eqhTcOj4R+uCFGBA+0JOPaTZT5GKsV/0RvNbP5VXcKVa+M60 Au+NIOd2ImuJyfyU24lLpYEqRQkTpmgqbLLf7rq1YfrHMdKHxMNTu4Xk+maSnu59CZfK b6j6UwnZZgT58TZkD0ZuzniD56CvHo8UNfMad79RW909/rNWrOpe8dC5e5qtEjqImv2R 6HO+6rT5l87Zb+Gn+D5LgogT1Gk3CNNWCl+SNIx8OeZpnCrE3Nfecv0LKhKnNij0y0Ak gVgAv6mePS4PRRBPAd2a+pt962fT0TwOgyMxQm2PRZVB6Iwya250GuqMWBhd6nzRE3+f sBjg== Received: by 10.180.108.45 with SMTP id hh13mr26072165wib.15.1350330538157; Mon, 15 Oct 2012 12:48:58 -0700 (PDT) Received: from localhost.localdomain (089144206171.atnat0015.highway.a1.net. [89.144.206.171]) by mx.google.com with ESMTPS id bn7sm17543324wib.8.2012.10.15.12.48.52 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 15 Oct 2012 12:48:57 -0700 (PDT) From: Richard Cochran To: Subject: [PATCH V2 3/7] cpsw: correct the CPSW_PORT register bank declaration Date: Mon, 15 Oct 2012 21:48:09 +0200 Message-Id: <88ec565ab25c47b397e8c423169faca5180c2307.1350329726.git.richardcochran@gmail.com> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: References: In-Reply-To: References: X-Spam-Note: CRM114 invocation failed X-Spam-Score: -2.7 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [74.125.82.49 listed in list.dnswl.org] 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (richardcochran[at]gmail.com) -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature Cc: Sriramakrishnan A G , Mugunthan V N , David Miller , linux-arm-kernel@lists.infradead.org, Cyril Chemparathy X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org This commit corrects and expands the slave port register bank according to TI's Technical Reference Manual. Signed-off-by: Richard Cochran --- Documentation/devicetree/bindings/net/cpsw.txt | 8 ++++---- arch/arm/boot/dts/am33xx.dtsi | 4 ++-- drivers/net/ethernet/ti/cpsw.c | 18 ++++++++++++++---- 3 files changed, 20 insertions(+), 10 deletions(-) diff --git a/Documentation/devicetree/bindings/net/cpsw.txt b/Documentation/devicetree/bindings/net/cpsw.txt index dcaabe9..3af47b7 100644 --- a/Documentation/devicetree/bindings/net/cpsw.txt +++ b/Documentation/devicetree/bindings/net/cpsw.txt @@ -59,14 +59,14 @@ Examples: mac_control = <0x20>; slaves = <2>; cpsw_emac0: slave@0 { - slave_reg_ofs = <0x208>; + slave_reg_ofs = <0x200>; sliver_reg_ofs = <0xd80>; phy_id = "davinci_mdio.16:00"; /* Filled in by U-Boot */ mac-address = [ 00 00 00 00 00 00 ]; }; cpsw_emac1: slave@1 { - slave_reg_ofs = <0x308>; + slave_reg_ofs = <0x300>; sliver_reg_ofs = <0xdc0>; phy_id = "davinci_mdio.16:01"; /* Filled in by U-Boot */ @@ -93,14 +93,14 @@ Examples: mac_control = <0x20>; slaves = <2>; cpsw_emac0: slave@0 { - slave_reg_ofs = <0x208>; + slave_reg_ofs = <0x200>; sliver_reg_ofs = <0xd80>; phy_id = "davinci_mdio.16:00"; /* Filled in by U-Boot */ mac-address = [ 00 00 00 00 00 00 ]; }; cpsw_emac1: slave@1 { - slave_reg_ofs = <0x308>; + slave_reg_ofs = <0x300>; sliver_reg_ofs = <0xdc0>; phy_id = "davinci_mdio.16:01"; /* Filled in by U-Boot */ diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index f6bea04..cd9b3b4 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -238,13 +238,13 @@ interrupts = <40 41 42 43>; ranges; cpsw_emac0: slave@0 { - slave_reg_ofs = <0x208>; + slave_reg_ofs = <0x200>; sliver_reg_ofs = <0xd80>; /* Filled in by U-Boot */ mac-address = [ 00 00 00 00 00 00 ]; }; cpsw_emac1: slave@1 { - slave_reg_ofs = <0x308>; + slave_reg_ofs = <0x300>; sliver_reg_ofs = <0xdc0>; /* Filled in by U-Boot */ mac-address = [ 00 00 00 00 00 00 ]; diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c index 1bdbb36..e29bb8f 100644 --- a/drivers/net/ethernet/ti/cpsw.c +++ b/drivers/net/ethernet/ti/cpsw.c @@ -157,16 +157,26 @@ struct cpsw_ss_regs { }; struct cpsw_slave_regs { + u32 control; + u32 res1; u32 max_blks; u32 blk_cnt; - u32 flow_thresh; + u32 tx_in_ctl; u32 port_vlan; u32 tx_pri_map; - u32 ts_ctl; - u32 ts_seq_ltype; - u32 ts_vlan; + u32 ts_seq_mtype; u32 sa_lo; u32 sa_hi; + u32 send_percent; + u32 res2; + u32 rx_dscp_pri_map0; + u32 rx_dscp_pri_map1; + u32 rx_dscp_pri_map2; + u32 rx_dscp_pri_map3; + u32 rx_dscp_pri_map4; + u32 rx_dscp_pri_map5; + u32 rx_dscp_pri_map6; + u32 rx_dscp_pri_map7; }; struct cpsw_host_regs {