From patchwork Mon Nov 14 12:49:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 13042281 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EC2BCC433FE for ; Mon, 14 Nov 2022 12:50:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ZY++MlMhoikB4BoCWuJxSoI3muzmcWyk54EGz8oQ680=; b=I0RmlSfPuuAjpJ TCWVRaJ2BsgNhyq9zjduQSSLGzl/uISYrAthJeDH0w3FyBjxAYaAZiOrHNzblu6GpuFtPhI89QrYG 04hFeLJD3fOPNX+ixejuuU1muUSKMEE2dScLbO6zjW6NXv3Rbowf9X/cNBa7MM+KGbZW8E2C9frts 2GZ0QZOSbYsxAx8nb00xwib/G9WWGlyUaxo/n10b61E/tUATA2TFWJd7WCUVldZUO8H41Q9lMa6Nv lzfNfIW7hSqHycB9U8da7zQMADvxIr+L7rRH25ESKFapJRxkQ/f4FsCLczcuo9QShGmYo72DxytHX he6xsFcV4EcfYmXQQotw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ouYu3-000vO9-43; Mon, 14 Nov 2022 12:49:31 +0000 Received: from laurent.telenet-ops.be ([2a02:1800:110:4::f00:19]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1ouYtn-000vDS-RU for linux-arm-kernel@lists.infradead.org; Mon, 14 Nov 2022 12:49:18 +0000 Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed10:9cda:b28b:1ded:8138]) by laurent.telenet-ops.be with bizsmtp id kCp62800V3NlhLw01Cp6VX; Mon, 14 Nov 2022 13:49:07 +0100 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.93) (envelope-from ) id 1ouYte-000UUE-Af; Mon, 14 Nov 2022 13:49:06 +0100 Received: from geert by rox.of.borg with local (Exim 4.93) (envelope-from ) id 1ouYtd-003gzS-4D; Mon, 14 Nov 2022 13:49:05 +0100 From: Geert Uytterhoeven To: Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Geert Uytterhoeven Subject: [PATCH 5/5] arm64: dts: renesas: r8a779g0: Add CA76 operating points Date: Mon, 14 Nov 2022 13:49:04 +0100 Message-Id: <8afb32f5dc123ebf2b941703483152ff0992191d.1668429870.git.geert+renesas@glider.be> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221114_044916_073950_6206A7C4 X-CRM114-Status: GOOD ( 11.42 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add operating points for running the Cortex-A76 CPU cores on R-Car V4H at various speeds, up to the Normal (1.7 GHz) performance mode. Based on a patch in the BSP by Tho Vu. Signed-off-by: Geert Uytterhoeven --- An operating point for the High Performance mode (1.8 GHz) is not added, as it is not yet supported by the clock driver, and thus was not tested. --- arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 31 +++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi index 9cbe337220ed4dfc..45d8d927ad2642f3 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi @@ -14,6 +14,33 @@ / { #address-cells = <2>; #size-cells = <2>; + cluster0_opp: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <825000>; + clock-latency-ns = <500000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <825000>; + clock-latency-ns = <500000>; + }; + opp-1500000000 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <825000>; + clock-latency-ns = <500000>; + }; + opp-1700000000 { + opp-hz = /bits/ 64 <1700000000>; + opp-microvolt = <825000>; + clock-latency-ns = <500000>; + opp-suspend; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -47,6 +74,7 @@ a76_0: cpu@0 { enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>; + operating-points-v2 = <&cluster0_opp>; }; a76_1: cpu@100 { @@ -58,6 +86,7 @@ a76_1: cpu@100 { enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>; + operating-points-v2 = <&cluster0_opp>; }; a76_2: cpu@10000 { @@ -69,6 +98,7 @@ a76_2: cpu@10000 { enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>; + operating-points-v2 = <&cluster0_opp>; }; a76_3: cpu@10100 { @@ -80,6 +110,7 @@ a76_3: cpu@10100 { enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>; + operating-points-v2 = <&cluster0_opp>; }; idle-states {