Message ID | 8f8592d6454c024c8f8b92e56c9009c65ad1d54a.1683034376.git.michal.simek@amd.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show
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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT044.mail.protection.outlook.com (10.13.173.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6363.20 via Frontend Transport; Tue, 2 May 2023 13:36:44 +0000 Received: from localhost (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Tue, 2 May 2023 08:36:42 -0500 From: Michal Simek <michal.simek@amd.com> To: <linux-kernel@vger.kernel.org>, <monstr@monstr.eu>, <michal.simek@xilinx.com>, <git@xilinx.com> CC: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>, "Harini Katakam" <harini.katakam@amd.com>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Laurent Pinchart <laurent.pinchart@ideasonboard.com>, Michael Grzeschik <m.grzeschik@pengutronix.de>, Piyush Mehta <piyush.mehta@xilinx.com>, "Radhey Shyam Pandey" <radhey.shyam.pandey@amd.com>, Rob Herring <robh+dt@kernel.org>, Robert Hancock <robert.hancock@calian.com>, Tanmay Shah <tanmay.shah@amd.com>, <devicetree@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org> Subject: [PATCH 08/23] arm64: zynqmp: Add resets property to sdhci nodes Date: Tue, 2 May 2023 15:35:36 +0200 Message-ID: <8f8592d6454c024c8f8b92e56c9009c65ad1d54a.1683034376.git.michal.simek@amd.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <cover.1683034376.git.michal.simek@amd.com> References: <cover.1683034376.git.michal.simek@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT044:EE_|DM6PR12MB4481:EE_ X-MS-Office365-Filtering-Correlation-Id: 24256c72-cbb6-4926-3cf8-08db4b124511 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" <linux-arm-kernel-bounces@lists.infradead.org> Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org |
Series |
arm64: zynqmp: Misc zynqmp changes
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expand
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On 5/10/23 09:02, Laurent Pinchart wrote: > Hi Michal, > > Thank you for the patch. > > On Tue, May 02, 2023 at 03:35:36PM +0200, Michal Simek wrote: >> From: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com> >> >> Add "resets" property to sdhci nodes. Resets property is used to reset the >> SD host controller when dynamic configuration support is enabled. >> >> Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com> >> Signed-off-by: Michal Simek <michal.simek@amd.com> > > Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Applied. M
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index a117294dc890..7bd3e816226a 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -755,6 +755,7 @@ sdhci0: mmc@ff160000 { #clock-cells = <1>; clock-output-names = "clk_out_sd0", "clk_in_sd0"; power-domains = <&zynqmp_firmware PD_SD_0>; + resets = <&zynqmp_reset ZYNQMP_RESET_SDIO0>; }; sdhci1: mmc@ff170000 { @@ -768,6 +769,7 @@ sdhci1: mmc@ff170000 { #clock-cells = <1>; clock-output-names = "clk_out_sd1", "clk_in_sd1"; power-domains = <&zynqmp_firmware PD_SD_1>; + resets = <&zynqmp_reset ZYNQMP_RESET_SDIO1>; }; smmu: iommu@fd800000 {