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[178.255.168.35]) by smtp.gmail.com with ESMTPSA id q26sm8041340ejr.97.2021.02.01.06.27.36 (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 01 Feb 2021 06:27:36 -0800 (PST) From: Michal Simek To: linux-kernel@vger.kernel.org, monstr@monstr.eu, michal.simek@xilinx.com, git@xilinx.com Subject: [PATCH] ARM: dts: zynq: Add address-cells property to interrupt controllers Date: Mon, 1 Feb 2021 15:27:35 +0100 Message-Id: <91e3405245c89f134676449cf3822285798d2ed2.1612189652.git.michal.simek@xilinx.com> X-Mailer: git-send-email 2.30.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210201_092739_137488_4640AEED X-CRM114-Status: GOOD ( 13.41 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andre Przywara , Rob Herring , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The commit 3eb619b2f7d8 ("scripts/dtc: Update to upstream version v1.6.0-11-g9d7888cbf19c") updated dtc version which also contained DTC commit "81e0919a3e21 checks: Add interrupt provider test" where reasons for this checking are mentioned as "A missing #address-cells property is less critical, but creates ambiguities when used in interrupt-map properties, so warn about this as well now." Add address-cells property to gic and gpio nodes to get rid of this warning. The similar change has been done for ZynqMP too. CC: Andre Przywara Signed-off-by: Michal Simek --- arch/arm/boot/dts/zynq-7000.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi index df9ad831cf05..c4810d58540b 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++ b/arch/arm/boot/dts/zynq-7000.dtsi @@ -133,6 +133,7 @@ can1: can@e0009000 { gpio0: gpio@e000a000 { compatible = "xlnx,zynq-gpio-1.0"; + #address-cells = <0>; #gpio-cells = <2>; clocks = <&clkc 42>; gpio-controller; @@ -168,6 +169,7 @@ i2c1: i2c@e0005000 { intc: interrupt-controller@f8f01000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; + #address-cells = <0>; interrupt-controller; reg = <0xF8F01000 0x1000>, <0xF8F00100 0x100>;