| Message ID | 946794e97ae2c36cd67c272099e8236a589efc28.1500043741.git-series.plaes@plaes.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, Jul 14, 2017 at 05:49:23PM +0300, Priit Laes wrote: > SATA clock on sun4i/sun7i is of type (parent) / M / 6 where > 6 is fixed post-divider. > > Signed-off-by: Priit Laes <plaes@plaes.org> > --- > drivers/clk/sunxi-ng/ccu_div.c | 15 +++++++++++++-- > drivers/clk/sunxi-ng/ccu_div.h | 3 ++- > 2 files changed, 15 insertions(+), 3 deletions(-) > > diff --git a/drivers/clk/sunxi-ng/ccu_div.c b/drivers/clk/sunxi-ng/ccu_div.c > index c0e5c10..744502a 100644 > --- a/drivers/clk/sunxi-ng/ccu_div.c > +++ b/drivers/clk/sunxi-ng/ccu_div.c > @@ -21,6 +21,9 @@ static unsigned long ccu_div_round_rate(struct ccu_mux_internal *mux, > { > struct ccu_div *cd = data; > > + if (cd->common.features & CCU_FEATURE_FIXED_POSTDIV) > + rate *= cd->fixed_post_div; > + > return divider_round_rate_parent(&cd->common.hw, parent, > rate, parent_rate, > cd->div.table, cd->div.width, You still haven't addressed the biggest issue with this patch, see: https://patchwork.kernel.org/patch/9825565/ Maxime
在 2017-07-17 16:52，Maxime Ripard 写道： > On Fri, Jul 14, 2017 at 05:49:23PM +0300, Priit Laes wrote: >> SATA clock on sun4i/sun7i is of type (parent) / M / 6 where >> 6 is fixed post-divider. >> >> Signed-off-by: Priit Laes <plaes@plaes.org> >> --- >> drivers/clk/sunxi-ng/ccu_div.c | 15 +++++++++++++-- >> drivers/clk/sunxi-ng/ccu_div.h | 3 ++- >> 2 files changed, 15 insertions(+), 3 deletions(-) >> >> diff --git a/drivers/clk/sunxi-ng/ccu_div.c >> b/drivers/clk/sunxi-ng/ccu_div.c >> index c0e5c10..744502a 100644 >> --- a/drivers/clk/sunxi-ng/ccu_div.c >> +++ b/drivers/clk/sunxi-ng/ccu_div.c >> @@ -21,6 +21,9 @@ static unsigned long ccu_div_round_rate(struct >> ccu_mux_internal *mux, >> { >> struct ccu_div *cd = data; >> >> + if (cd->common.features & CCU_FEATURE_FIXED_POSTDIV) >> + rate *= cd->fixed_post_div; >> + >> return divider_round_rate_parent(&cd->common.hw, parent, >> rate, parent_rate, >> cd->div.table, cd->div.width, > > > You still haven't addressed the biggest issue with this patch, see: > https://patchwork.kernel.org/patch/9825565/ I think he has already did the changes suggested in the review. (P.S. during developing R40 CCU driver I found that pll-periph0-sata also needs this patch, so I'm rechecking it) > > Maxime > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
On Sat, Aug 12, 2017 at 11:07 AM, <icenowy@aosc.io> wrote: > 在 2017-07-17 16:52，Maxime Ripard 写道： >> >> On Fri, Jul 14, 2017 at 05:49:23PM +0300, Priit Laes wrote: >>> >>> SATA clock on sun4i/sun7i is of type (parent) / M / 6 where >>> 6 is fixed post-divider. >>> >>> Signed-off-by: Priit Laes <plaes@plaes.org> >>> --- >>> drivers/clk/sunxi-ng/ccu_div.c | 15 +++++++++++++-- >>> drivers/clk/sunxi-ng/ccu_div.h | 3 ++- >>> 2 files changed, 15 insertions(+), 3 deletions(-) >>> >>> diff --git a/drivers/clk/sunxi-ng/ccu_div.c >>> b/drivers/clk/sunxi-ng/ccu_div.c >>> index c0e5c10..744502a 100644 >>> --- a/drivers/clk/sunxi-ng/ccu_div.c >>> +++ b/drivers/clk/sunxi-ng/ccu_div.c >>> @@ -21,6 +21,9 @@ static unsigned long ccu_div_round_rate(struct >>> ccu_mux_internal *mux, >>> { >>> struct ccu_div *cd = data; >>> >>> + if (cd->common.features & CCU_FEATURE_FIXED_POSTDIV) >>> + rate *= cd->fixed_post_div; >>> + >>> return divider_round_rate_parent(&cd->common.hw, parent, >>> rate, parent_rate, >>> cd->div.table, cd->div.width, >> >> >> >> You still haven't addressed the biggest issue with this patch, see: >> https://patchwork.kernel.org/patch/9825565/ > > > I think he has already did the changes suggested in the review. Nope. Only half of it is fixed. First you "unapply" the post-divider, i.e. multiply the rate by the divider. Then you pass it to divider_round_rate_parent. You still have to reapply the divider to the result. This last part is missing. This means the clock rate returned by ccu_div_round_rate is going to be off. Instead the return statement should be return divider_round_rate_parent(...) / cd->fixed_post_div ChenYu > > (P.S. during developing R40 CCU driver I found that pll-periph0-sata > also needs this patch, so I'm rechecking it) > >> >> Maxime >> >> _______________________________________________ >> linux-arm-kernel mailing list >> linux-arm-kernel@lists.infradead.org >> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel > > > -- > You received this message because you are subscribed to the Google Groups > "linux-sunxi" group. > To unsubscribe from this group and stop receiving emails from it, send an > email to linux-sunxi+unsubscribe@googlegroups.com. > For more options, visit https://groups.google.com/d/optout.
在 2017-08-12 12:13，Chen-Yu Tsai 写道： > On Sat, Aug 12, 2017 at 11:07 AM, <icenowy@aosc.io> wrote: >> 在 2017-07-17 16:52，Maxime Ripard 写道： >>> >>> On Fri, Jul 14, 2017 at 05:49:23PM +0300, Priit Laes wrote: >>>> >>>> SATA clock on sun4i/sun7i is of type (parent) / M / 6 where >>>> 6 is fixed post-divider. >>>> >>>> Signed-off-by: Priit Laes <plaes@plaes.org> >>>> --- >>>> drivers/clk/sunxi-ng/ccu_div.c | 15 +++++++++++++-- >>>> drivers/clk/sunxi-ng/ccu_div.h | 3 ++- >>>> 2 files changed, 15 insertions(+), 3 deletions(-) >>>> >>>> diff --git a/drivers/clk/sunxi-ng/ccu_div.c >>>> b/drivers/clk/sunxi-ng/ccu_div.c >>>> index c0e5c10..744502a 100644 >>>> --- a/drivers/clk/sunxi-ng/ccu_div.c >>>> +++ b/drivers/clk/sunxi-ng/ccu_div.c >>>> @@ -21,6 +21,9 @@ static unsigned long ccu_div_round_rate(struct >>>> ccu_mux_internal *mux, >>>> { >>>> struct ccu_div *cd = data; >>>> >>>> + if (cd->common.features & CCU_FEATURE_FIXED_POSTDIV) >>>> + rate *= cd->fixed_post_div; >>>> + >>>> return divider_round_rate_parent(&cd->common.hw, parent, >>>> rate, parent_rate, >>>> cd->div.table, >>>> cd->div.width, >>> >>> >>> >>> You still haven't addressed the biggest issue with this patch, see: >>> https://patchwork.kernel.org/patch/9825565/ >> >> >> I think he has already did the changes suggested in the review. > > Nope. Only half of it is fixed. First you "unapply" the post-divider, > i.e. multiply the rate by the divider. Then you pass it to > divider_round_rate_parent. You still have to reapply the divider > to the result. This last part is missing. This means the clock > rate returned by ccu_div_round_rate is going to be off. > > Instead the return statement should be > > return divider_round_rate_parent(...) / cd->fixed_post_div Oh, got it by reading other CCU clock types that has fixed postdiv. Thanks! > > ChenYu > >> >> (P.S. during developing R40 CCU driver I found that pll-periph0-sata >> also needs this patch, so I'm rechecking it) >> >>> >>> Maxime >>> >>> _______________________________________________ >>> linux-arm-kernel mailing list >>> linux-arm-kernel@lists.infradead.org >>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel >> >> >> -- >> You received this message because you are subscribed to the Google >> Groups >> "linux-sunxi" group. >> To unsubscribe from this group and stop receiving emails from it, send >> an >> email to linux-sunxi+unsubscribe@googlegroups.com. >> For more options, visit https://groups.google.com/d/optout. > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
diff --git a/drivers/clk/sunxi-ng/ccu_div.c b/drivers/clk/sunxi-ng/ccu_div.c index c0e5c10..744502a 100644 --- a/drivers/clk/sunxi-ng/ccu_div.c +++ b/drivers/clk/sunxi-ng/ccu_div.c @@ -21,6 +21,9 @@ static unsigned long ccu_div_round_rate(struct ccu_mux_internal *mux, { struct ccu_div *cd = data; + if (cd->common.features & CCU_FEATURE_FIXED_POSTDIV) + rate *= cd->fixed_post_div; + return divider_round_rate_parent(&cd->common.hw, parent, rate, parent_rate, cd->div.table, cd->div.width, @@ -62,8 +65,13 @@ static unsigned long ccu_div_recalc_rate(struct clk_hw *hw, parent_rate = ccu_mux_helper_apply_prediv(&cd->common, &cd->mux, -1, parent_rate); - return divider_recalc_rate(hw, parent_rate, val, cd->div.table, - cd->div.flags); + val = divider_recalc_rate(hw, parent_rate, val, cd->div.table, + cd->div.flags); + + if (cd->common.features & CCU_FEATURE_FIXED_POSTDIV) + val /= cd->fixed_post_div; + + return val; } static int ccu_div_determine_rate(struct clk_hw *hw, @@ -86,6 +94,9 @@ static int ccu_div_set_rate(struct clk_hw *hw, unsigned long rate, parent_rate = ccu_mux_helper_apply_prediv(&cd->common, &cd->mux, -1, parent_rate); + if (cd->common.features & CCU_FEATURE_FIXED_POSTDIV) + rate *= cd->fixed_post_div; + val = divider_get_val(rate, parent_rate, cd->div.table, cd->div.width, cd->div.flags); diff --git a/drivers/clk/sunxi-ng/ccu_div.h b/drivers/clk/sunxi-ng/ccu_div.h index 08d0744..f3a5028 100644 --- a/drivers/clk/sunxi-ng/ccu_div.h +++ b/drivers/clk/sunxi-ng/ccu_div.h @@ -86,9 +86,10 @@ struct ccu_div_internal { struct ccu_div { u32 enable; - struct ccu_div_internal div; + struct ccu_div_internal div; struct ccu_mux_internal mux; struct ccu_common common; + unsigned int fixed_post_div; }; #define SUNXI_CCU_DIV_TABLE_WITH_GATE(_struct, _name, _parent, _reg, \
SATA clock on sun4i/sun7i is of type (parent) / M / 6 where 6 is fixed post-divider. Signed-off-by: Priit Laes <plaes@plaes.org> --- drivers/clk/sunxi-ng/ccu_div.c | 15 +++++++++++++-- drivers/clk/sunxi-ng/ccu_div.h | 3 ++- 2 files changed, 15 insertions(+), 3 deletions(-)