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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , xfr@outlook.com, Furong Xu <0x1207@gmail.com> Subject: [PATCH net-next v1 3/5] net: stmmac: Rework marco definitions for gmac4 and xgmac Date: Tue, 15 Oct 2024 17:09:24 +0800 Message-Id: <94705afa1d2815e82c27d3d1a13b2ad6ada8952f.1728980110.git.0x1207@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241015_101019_109547_4CDB1CC3 X-CRM114-Status: GOOD ( 18.42 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Rename and add marco definitions to better reuse them in common code. Signed-off-by: Furong Xu <0x1207@gmail.com> Reviewed-by: Simon Horman --- .../net/ethernet/stmicro/stmmac/stmmac_fpe.c | 49 ++++++++++--------- .../net/ethernet/stmicro/stmmac/stmmac_fpe.h | 26 +++++----- 2 files changed, 38 insertions(+), 37 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.c index c01eb7243d56..0c13d5aee3d2 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.c @@ -168,7 +168,7 @@ static void dwmac5_fpe_configure(void __iomem *ioaddr, u32 value; if (tx_enable) { - cfg->fpe_csr = EFPE; + cfg->fpe_csr = STMMAC_MAC_FPE_CTRL_STS_EFPE; value = readl(ioaddr + GMAC_RXQ_CTRL1); value &= ~GMAC_RXQCTRL_FPRQ; value |= (num_rxq - 1) << GMAC_RXQCTRL_FPRQ_SHIFT; @@ -176,14 +176,14 @@ static void dwmac5_fpe_configure(void __iomem *ioaddr, } else { cfg->fpe_csr = 0; } - writel(cfg->fpe_csr, ioaddr + MAC_FPE_CTRL_STS); + writel(cfg->fpe_csr, ioaddr + GMAC5_MAC_FPE_CTRL_STS); value = readl(ioaddr + GMAC_INT_EN); if (pmac_enable) { if (!(value & GMAC_INT_FPE_EN)) { /* Dummy read to clear any pending masked interrupts */ - readl(ioaddr + MAC_FPE_CTRL_STS); + readl(ioaddr + GMAC5_MAC_FPE_CTRL_STS); value |= GMAC_INT_FPE_EN; } @@ -204,24 +204,24 @@ static int dwmac5_fpe_irq_status(void __iomem *ioaddr, struct net_device *dev) /* Reads from the MAC_FPE_CTRL_STS register should only be performed * here, since the status flags of MAC_FPE_CTRL_STS are "clear on read" */ - value = readl(ioaddr + MAC_FPE_CTRL_STS); + value = readl(ioaddr + GMAC5_MAC_FPE_CTRL_STS); - if (value & TRSP) { + if (value & STMMAC_MAC_FPE_CTRL_STS_TRSP) { status |= FPE_EVENT_TRSP; netdev_dbg(dev, "FPE: Respond mPacket is transmitted\n"); } - if (value & TVER) { + if (value & STMMAC_MAC_FPE_CTRL_STS_TVER) { status |= FPE_EVENT_TVER; netdev_dbg(dev, "FPE: Verify mPacket is transmitted\n"); } - if (value & RRSP) { + if (value & STMMAC_MAC_FPE_CTRL_STS_RRSP) { status |= FPE_EVENT_RRSP; netdev_dbg(dev, "FPE: Respond mPacket is received\n"); } - if (value & RVER) { + if (value & STMMAC_MAC_FPE_CTRL_STS_RVER) { status |= FPE_EVENT_RVER; netdev_dbg(dev, "FPE: Verify mPacket is received\n"); } @@ -236,16 +236,17 @@ static void dwmac5_fpe_send_mpacket(void __iomem *ioaddr, u32 value = cfg->fpe_csr; if (type == MPACKET_VERIFY) - value |= SVER; + value |= STMMAC_MAC_FPE_CTRL_STS_SVER; else if (type == MPACKET_RESPONSE) - value |= SRSP; + value |= STMMAC_MAC_FPE_CTRL_STS_SRSP; - writel(value, ioaddr + MAC_FPE_CTRL_STS); + writel(value, ioaddr + GMAC5_MAC_FPE_CTRL_STS); } static int dwmac5_fpe_get_add_frag_size(const void __iomem *ioaddr) { - return FIELD_GET(DWMAC5_ADD_FRAG_SZ, readl(ioaddr + MTL_FPE_CTRL_STS)); + return FIELD_GET(FPE_MTL_ADD_FRAG_SZ, + readl(ioaddr + GMAC5_MTL_FPE_CTRL_STS)); } static void dwmac5_fpe_set_add_frag_size(void __iomem *ioaddr, @@ -253,9 +254,9 @@ static void dwmac5_fpe_set_add_frag_size(void __iomem *ioaddr, { u32 value; - value = readl(ioaddr + MTL_FPE_CTRL_STS); - writel(u32_replace_bits(value, add_frag_size, DWMAC5_ADD_FRAG_SZ), - ioaddr + MTL_FPE_CTRL_STS); + value = readl(ioaddr + GMAC5_MTL_FPE_CTRL_STS); + writel(u32_replace_bits(value, add_frag_size, FPE_MTL_ADD_FRAG_SZ), + ioaddr + GMAC5_MTL_FPE_CTRL_STS); } #define ALG_ERR_MSG "TX algorithm SP is not suitable for one-to-many mapping" @@ -307,9 +308,9 @@ static int dwmac5_fpe_map_preemption_class(struct net_device *ndev, } update_mapping: - val = readl(priv->ioaddr + MTL_FPE_CTRL_STS); - writel(u32_replace_bits(val, preemptible_txqs, DWMAC5_PREEMPTION_CLASS), - priv->ioaddr + MTL_FPE_CTRL_STS); + val = readl(priv->ioaddr + GMAC5_MTL_FPE_CTRL_STS); + writel(u32_replace_bits(val, preemptible_txqs, FPE_MTL_PREEMPTION_CLASS), + priv->ioaddr + GMAC5_MTL_FPE_CTRL_STS); return 0; } @@ -322,11 +323,11 @@ static void dwxgmac3_fpe_configure(void __iomem *ioaddr, u32 value; if (!tx_enable) { - value = readl(ioaddr + XGMAC_FPE_CTRL_STS); + value = readl(ioaddr + XGMAC_MAC_FPE_CTRL_STS); - value &= ~XGMAC_EFPE; + value &= ~STMMAC_MAC_FPE_CTRL_STS_EFPE; - writel(value, ioaddr + XGMAC_FPE_CTRL_STS); + writel(value, ioaddr + XGMAC_MAC_FPE_CTRL_STS); return; } @@ -335,9 +336,9 @@ static void dwxgmac3_fpe_configure(void __iomem *ioaddr, value |= (num_rxq - 1) << XGMAC_RQ_SHIFT; writel(value, ioaddr + XGMAC_RXQ_CTRL1); - value = readl(ioaddr + XGMAC_FPE_CTRL_STS); - value |= XGMAC_EFPE; - writel(value, ioaddr + XGMAC_FPE_CTRL_STS); + value = readl(ioaddr + XGMAC_MAC_FPE_CTRL_STS); + value |= STMMAC_MAC_FPE_CTRL_STS_EFPE; + writel(value, ioaddr + XGMAC_MAC_FPE_CTRL_STS); } const struct stmmac_fpe_ops dwmac5_fpe_ops = { diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.h b/drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.h index a113b5c57de9..c0305f11575b 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.h +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.h @@ -8,23 +8,23 @@ #define STMMAC_FPE_MM_MAX_VERIFY_RETRIES 3 #define STMMAC_FPE_MM_MAX_VERIFY_TIME_MS 128 -#define MAC_FPE_CTRL_STS 0x00000234 -#define TRSP BIT(19) -#define TVER BIT(18) -#define RRSP BIT(17) -#define RVER BIT(16) -#define SRSP BIT(2) -#define SVER BIT(1) -#define EFPE BIT(0) +#define GMAC5_MAC_FPE_CTRL_STS 0x00000234 +#define XGMAC_MAC_FPE_CTRL_STS 0x00000280 -#define MTL_FPE_CTRL_STS 0x00000c90 +#define GMAC5_MTL_FPE_CTRL_STS 0x00000c90 +#define XGMAC_MTL_FPE_CTRL_STS 0x00001090 /* Preemption Classification */ -#define DWMAC5_PREEMPTION_CLASS GENMASK(15, 8) +#define FPE_MTL_PREEMPTION_CLASS GENMASK(15, 8) /* Additional Fragment Size of preempted frames */ -#define DWMAC5_ADD_FRAG_SZ GENMASK(1, 0) +#define FPE_MTL_ADD_FRAG_SZ GENMASK(1, 0) -#define XGMAC_FPE_CTRL_STS 0x00000280 -#define XGMAC_EFPE BIT(0) +#define STMMAC_MAC_FPE_CTRL_STS_TRSP BIT(19) +#define STMMAC_MAC_FPE_CTRL_STS_TVER BIT(18) +#define STMMAC_MAC_FPE_CTRL_STS_RRSP BIT(17) +#define STMMAC_MAC_FPE_CTRL_STS_RVER BIT(16) +#define STMMAC_MAC_FPE_CTRL_STS_SRSP BIT(2) +#define STMMAC_MAC_FPE_CTRL_STS_SVER BIT(1) +#define STMMAC_MAC_FPE_CTRL_STS_EFPE BIT(0) /* FPE link-partner hand-shaking mPacket type */ enum stmmac_mpacket_type {