From patchwork Mon Oct 8 05:37:46 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Afzal Mohammed X-Patchwork-Id: 1563821 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id A9922DFFAD for ; Mon, 8 Oct 2012 05:44:41 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TL66V-0006s6-RC; Mon, 08 Oct 2012 05:42:12 +0000 Received: from devils.ext.ti.com ([198.47.26.153]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1TL62K-0003oZ-TP; Mon, 08 Oct 2012 05:37:54 +0000 Received: from dbdp20.itg.ti.com ([172.24.170.38]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id q985blFW032635; Mon, 8 Oct 2012 00:37:48 -0500 Received: from DBDE70.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id q985bldg016165; Mon, 8 Oct 2012 11:07:47 +0530 (IST) Received: from dbdp32.itg.ti.com (172.24.170.251) by dbde70.ent.ti.com (172.24.170.148) with Microsoft SMTP Server id 14.1.323.3; Mon, 8 Oct 2012 11:07:47 +0530 Received: from psplinux063.india.ti.com (dbdp20.itg.ti.com [172.24.170.38]) by dbdp32.itg.ti.com (8.13.8/8.13.8) with ESMTP id q985blcU004305; Mon, 8 Oct 2012 11:07:47 +0530 From: Afzal Mohammed To: Tony Lindgren , Artem Bityutskiy Subject: [PATCH v2 10/14] ARM: OMAP2+: nand: bch capability check Date: Mon, 8 Oct 2012 11:07:46 +0530 Message-ID: <9575950c712e397fa9ddca535d167e6c77e1934d.1349672877.git.afzal@ti.com> X-Mailer: git-send-email 1.7.12 In-Reply-To: References: MIME-Version: 1.0 X-Spam-Note: CRM114 invocation failed X-Spam-Score: -9.0 (---------) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-9.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [198.47.26.153 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -2.1 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Paul Walmsley , Afzal Mohammed , linux-mtd@lists.infradead.org, Jon Hunter , Ivan Djelic , linux-omap@vger.kernel.org, David Woodhouse , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Capability of bch schemes could be discovered using soc revision checks. If soc revision indicates that selected ecc scheme is not supported bail out. Signed-off-by: Afzal Mohammed --- arch/arm/mach-omap2/gpmc-nand.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c index c1b9b1d..7983d54 100644 --- a/arch/arm/mach-omap2/gpmc-nand.c +++ b/arch/arm/mach-omap2/gpmc-nand.c @@ -90,6 +90,27 @@ static int omap2_nand_gpmc_retime( return 0; } +static bool __init gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt) +{ + /* support only OMAP3 class */ + if (!cpu_is_omap34xx()) { + pr_err("BCH ecc is not supported on this CPU\n"); + return 0; + } + + /* + * For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1. + * Other chips may be added if confirmed to work. + */ + if ((ecc_opt == OMAP_ECC_BCH4_CODE_HW) && + (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0))) { + pr_err("BCH 4-bit mode is not supported on this CPU\n"); + return 0; + } + + return 1; +} + int __init gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data, struct gpmc_timings *gpmc_t) { @@ -128,6 +149,9 @@ int __init gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data, gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs); + if (!gpmc_hwecc_bch_capable(gpmc_nand_data->ecc_opt)) + return -EINVAL; + err = platform_device_register(&gpmc_nand_device); if (err < 0) { dev_err(dev, "Unable to register NAND device\n");