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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000EDD6.mail.protection.outlook.com (10.167.241.210) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7025.20 via Frontend Transport; Thu, 23 Nov 2023 07:03:15 +0000 Received: from localhost (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Thu, 23 Nov 2023 01:02:34 -0600 From: Michal Simek To: , , , , , CC: Krzysztof Kozlowski , Conor Dooley , Damien Le Moal , Jassi Brar , Krzysztof Kozlowski , Mark Brown , Rob Herring , , Subject: [PATCH v4 1/2] dt-bindings: soc: xilinx: Move xilinx.yaml from arm to soc Date: Thu, 23 Nov 2023 08:02:27 +0100 Message-ID: <9653338d293c25ff0e591213698d59ac55cf5c27.1700722941.git.michal.simek@amd.com> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-Developer-Signature: v=1; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Nov 2023 07:03:15.4368 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5272d39e-70a0-4ad8-8e91-08dbebf243eb X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EDD6.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8219 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231122_230330_287468_AF95A275 X-CRM114-Status: GOOD ( 13.77 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org All Xilinx boards can hosts also soft core CPUs like MicroBlaze or MicroBlaze V (RISC-V ISA) that's why move boards description from arm folder to soc folder. Similar change was done for Renesas by commit c27ce08b806d ("dt-bindings: soc: renesas: Move renesas.yaml from arm to soc"). Signed-off-by: Michal Simek Acked-by: Krzysztof Kozlowski --- Changes in v4: - s/chagne/change/ in commit message - Fix binding location Changes in v3: - Fix commit message reported by Krzysztof and add his ACK Changes in v2: - New patch in the series Based on discussion here. https://lore.kernel.org/r/20231108-copper-scoff-b4de5febb954@spud --- .../devicetree/bindings/{arm => soc/xilinx}/xilinx.yaml | 2 +- MAINTAINERS | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) rename Documentation/devicetree/bindings/{arm => soc/xilinx}/xilinx.yaml (98%) diff --git a/Documentation/devicetree/bindings/arm/xilinx.yaml b/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml similarity index 98% rename from Documentation/devicetree/bindings/arm/xilinx.yaml rename to Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml index f57ed0347894..95758deca325 100644 --- a/Documentation/devicetree/bindings/arm/xilinx.yaml +++ b/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 %YAML 1.2 --- -$id: http://devicetree.org/schemas/arm/xilinx.yaml# +$id: http://devicetree.org/schemas/soc/xilinx/xilinx.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Xilinx Zynq Platforms diff --git a/MAINTAINERS b/MAINTAINERS index ea790149af79..14ad00009a63 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3020,6 +3020,7 @@ F: Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml F: Documentation/devicetree/bindings/i2c/xlnx,xps-iic-2.00.a.yaml F: Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml F: Documentation/devicetree/bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml +F: Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml F: Documentation/devicetree/bindings/spi/xlnx,zynq-qspi.yaml F: arch/arm/mach-zynq/ F: drivers/clocksource/timer-cadence-ttc.c