[v5,26/27] clk: bcm2835: Don't cache the PLLB rate

Commit Message

Maxime Ripard June 15, 2020, 8:41 a.m. UTC

The PLLB rate will be changed through the firmware clocks drivers and will
change behind this drivers' back, so we don't want to cache the rate.

Acked-by: Nicolas Saenz Julienne <[e-mail]>
Tested-by: Nicolas Saenz Julienne <[e-mail]>
Signed-off-by: Maxime Ripard <[e-mail]>
---
 drivers/clk/bcm/clk-bcm2835.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

Comments

Stephen Boyd June 25, 2020, 12:46 a.m. UTC | #1

Quoting Maxime Ripard (2020-06-15 01:41:06)
> The PLLB rate will be changed through the firmware clocks drivers and will
> change behind this drivers' back, so we don't want to cache the rate.
> 
> Acked-by: Nicolas Saenz Julienne <[e-mail]>
> Tested-by: Nicolas Saenz Julienne <[e-mail]>
> Signed-off-by: Maxime Ripard <[e-mail]>
> ---

Applied to clk-next

Patch

diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
index b50f00f109bf..027eba31f793 100644
--- a/drivers/clk/bcm/clk-bcm2835.c
+++ b/drivers/clk/bcm/clk-bcm2835.c
@@ -1700,7 +1700,8 @@  static const struct bcm2835_clk_desc clk_desc_array[] = {
 
 		.min_rate = 600000000u,
 		.max_rate = 3000000000u,
-		.max_fb_rate = BCM2835_MAX_FB_RATE),
+		.max_fb_rate = BCM2835_MAX_FB_RATE,
+		.flags = CLK_GET_RATE_NOCACHE),
 	[BCM2835_PLLB_ARM]	= REGISTER_PLL_DIV(
 		SOC_ALL,
 		.name = "pllb_arm",
@@ -1710,7 +1711,7 @@  static const struct bcm2835_clk_desc clk_desc_array[] = {
 		.load_mask = CM_PLLB_LOADARM,
 		.hold_mask = CM_PLLB_HOLDARM,
 		.fixed_divider = 1,
-		.flags = CLK_SET_RATE_PARENT),
+		.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE),
 
 	/*
 	 * PLLC is the core PLL, used to drive the core VPU clock.