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Tue, 6 Aug 2024 19:11:58 -0700 From: Nicolin Chen To: CC: , , , , , , , , , Subject: [PATCH v11 2/9] iommu/arm-smmu-v3: Enforce arm_smmu_cmdq_build_sync_cmd Date: Tue, 6 Aug 2024 19:11:47 -0700 Message-ID: <9e59a460c969357a98b3434ed5007ddf9381899b.1722993435.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF00036F3D:EE_|SN7PR12MB6789:EE_ X-MS-Office365-Filtering-Correlation-Id: d9d8f44e-3594-4203-7728-08dcb6865a73 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|36860700013; X-Microsoft-Antispam-Message-Info: JlGxJVC3kBttyqQ4hkp3UXOuIq299k8XWlOyv2PWqjYeVjKntf45CDPRGt0V+4ppXxYHaGol2pIrIqDtEDcJ9cttBuPgWo/0+QyQapApvoJigJsAYrheYsx6rXyHaqq12jhHyTR73b6cJ5Fzw4hZVyg7XTtH0PcqH9qvx6fj5JV15olvxaNQaiyfvmBfDyc2v4nyH+VjVaKzLwDLxxd3skrl64HruV/pk58dAUk5KgBxmmrcmiHT4sl/zPze8kRptWeWr2DHtfchesD3jjw4t1nggkt0ufalHcul87Andyvku0X5TEp0ZA6LXWAzs0LobNEVFv9V5jDoaKRGF/uw2IV3dkjgVoys9cUsb56xG4UhRl9ylJkjTwQZgp3UJLLzH9JhmN4i7WfWJT75+Sii/n4OeXBDwxCpi8gWhIM/MBnQlsZ7kUQQ/saR+qNxhQL6oNd+3U28KfgrYOr1IyXaj15PNZNT+blOYMLibzqqMo/pqi0N2z4ULki7d/s2YdgbYC+fYt0YgZQEZtLFeoRIxCl5J+Je54dkjPjb3riqtLlL4I6Vp6QGkVH+vsk+Qo6XF4D+z1qSyublR+AzBD4uhanVW3AnSg6TV/bgWsLx/JmWetpWNiEUzIq7QDb9z1D4DI8b+qUy4J7Git5EJuT4CDPc2CrbovEcSXGXRIMKAaYtFt4hWOwdd8rcghoCTNVTbIkaCkkRt+gRXj8Rw51PEnbhg+NwUqIrjWzKBsle3jMvEZSs4fw5X+aw5Qwp/R1EcLPucT0G/JB7Qs+qYWOxN30Lbml+uUja0O1Y2swhvIiusEm6AknxeNnDGYUHv/U8AOWltAVxdS5N634x7rtz6gLYjc4xkfKNwKnFBAvx5VyZ8OmAcIkeqvW9JF5lQBwoi8DpQAXY85bDe90WnmcN3VtXgghPp/mOsyl/G1YRapsUpTLpQNGISeG9LJorOil1NpQIph0G6MLMKg/EtzWeSEK4BWgPz/tE3sotfSbSsUgaaR8W+wo4QESzFnQuo3UnA2QKAIrHHkklynuyqQ+nsi2nFD09wweSmI9/dizOeuI2VuRdBRb50doUANQ/6SbyhlG48zTAXyFhv4UF6ushUSzdHcMw0DTb55yVSqLEPjGnGuOyiP8xWqaUU8bD/hgTJVMQuQ7WXpwykOdedJ1Ua0DXKixZrviY+UMSBG/tTkEzpeB2e0ZTW1WjQKJ2kwgtBa7g+qhGgiRQxyjdgTD908Oqp+A0XWB+rnK3ql/z8vN1jxguxM38EtViA3pR2YeaC2yD6uTxTgsVPXEPFjVstdYrNn1BWef3DF2EybBaTrJrXCFz1yl7wXoGCZu9WEbG4ESRc/yRkilZ2Ng5rcglNHs/pagZGxVk28N0AG1WBhKR1tqZRFlBSD92nToJfH3XwUgMzCuIvpp8j/92dk2Vw84PWF8yj+B7ozPXsoGuxH5qU2mHisMP+pVr4GF7gKCs X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(376014)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Aug 2024 02:12:13.7751 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d9d8f44e-3594-4203-7728-08dcb6865a73 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF00036F3D.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB6789 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240806_191227_074378_1A69154A X-CRM114-Status: GOOD ( 17.24 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org There is an existing arm_smmu_cmdq_build_sync_cmd() so the driver should call it at all places other than going through arm_smmu_cmdq_build_cmd() separately. This helps the following patch that adds a CS_NONE option. Note that this changes the type of CMD_SYNC in __arm_smmu_cmdq_skip_err, in ARM_SMMU_OPT_MSIPOLL=true case, from previously a non-MSI one to now an MSI one that is proven to still work using a hacking test: nvme: Adding to iommu group 10 nvme: --------hacking----------- arm-smmu-v3: unexpected global error reported (0x00000001), this could be serious arm-smmu-v3: CMDQ error (cons 0x01000022): Illegal command arm-smmu-v3: skipping command in error state: arm-smmu-v3: 0x0000000000000000 arm-smmu-v3: 0x0000000000000000 nvme: -------recovered---------- nvme nvme0: 72/0/0 default/read/poll queues nvme0n1: p1 p2 Suggested-by: Jason Gunthorpe Reviewed-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 36 ++++++++------------- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 3 -- 2 files changed, 13 insertions(+), 26 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index f409ead589ff..f481d7be3d4e 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -329,16 +329,6 @@ static int arm_smmu_cmdq_build_cmd(u64 *cmd, struct arm_smmu_cmdq_ent *ent) cmd[0] |= FIELD_PREP(CMDQ_RESUME_0_RESP, ent->resume.resp); cmd[1] |= FIELD_PREP(CMDQ_RESUME_1_STAG, ent->resume.stag); break; - case CMDQ_OP_CMD_SYNC: - if (ent->sync.msiaddr) { - cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_IRQ); - cmd[1] |= ent->sync.msiaddr & CMDQ_SYNC_1_MSIADDR_MASK; - } else { - cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_SEV); - } - cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_MSH, ARM_SMMU_SH_ISH); - cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_MSIATTR, ARM_SMMU_MEMATTR_OIWB); - break; default: return -ENOENT; } @@ -354,20 +344,23 @@ static struct arm_smmu_cmdq *arm_smmu_get_cmdq(struct arm_smmu_device *smmu) static void arm_smmu_cmdq_build_sync_cmd(u64 *cmd, struct arm_smmu_device *smmu, struct arm_smmu_queue *q, u32 prod) { - struct arm_smmu_cmdq_ent ent = { - .opcode = CMDQ_OP_CMD_SYNC, - }; + cmd[1] = 0; + cmd[0] = FIELD_PREP(CMDQ_0_OP, CMDQ_OP_CMD_SYNC) | + FIELD_PREP(CMDQ_SYNC_0_MSH, ARM_SMMU_SH_ISH) | + FIELD_PREP(CMDQ_SYNC_0_MSIATTR, ARM_SMMU_MEMATTR_OIWB); + + if (!(smmu->options & ARM_SMMU_OPT_MSIPOLL)) { + cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_SEV); + return; + } /* * Beware that Hi16xx adds an extra 32 bits of goodness to its MSI * payload, so the write will zero the entire command on that platform. */ - if (smmu->options & ARM_SMMU_OPT_MSIPOLL) { - ent.sync.msiaddr = q->base_dma + Q_IDX(&q->llq, prod) * - q->ent_dwords * 8; - } - - arm_smmu_cmdq_build_cmd(cmd, &ent); + cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_IRQ); + cmd[1] |= (q->base_dma + Q_IDX(&q->llq, prod) * q->ent_dwords * 8) & + CMDQ_SYNC_1_MSIADDR_MASK; } static void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu, @@ -384,9 +377,6 @@ static void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu, u64 cmd[CMDQ_ENT_DWORDS]; u32 cons = readl_relaxed(q->cons_reg); u32 idx = FIELD_GET(CMDQ_CONS_ERR, cons); - struct arm_smmu_cmdq_ent cmd_sync = { - .opcode = CMDQ_OP_CMD_SYNC, - }; dev_err(smmu->dev, "CMDQ error (cons 0x%08x): %s\n", cons, idx < ARRAY_SIZE(cerror_str) ? cerror_str[idx] : "Unknown"); @@ -420,7 +410,7 @@ static void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu, dev_err(smmu->dev, "\t0x%016llx\n", (unsigned long long)cmd[i]); /* Convert the erroneous command into a CMD_SYNC */ - arm_smmu_cmdq_build_cmd(cmd, &cmd_sync); + arm_smmu_cmdq_build_sync_cmd(cmd, smmu, q, cons); queue_write(Q_ENT(q, cons), cmd, q->ent_dwords); } diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index c1454e9758c4..6c5739f6b90f 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -518,9 +518,6 @@ struct arm_smmu_cmdq_ent { } resume; #define CMDQ_OP_CMD_SYNC 0x46 - struct { - u64 msiaddr; - } sync; }; };