From patchwork Fri Apr 22 15:56:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: icenowy@outlook.com X-Patchwork-Id: 12823707 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D3D29C4332F for ; Fri, 22 Apr 2022 16:01:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=p/I85JzKc7EOHE775srv+eHQcA82cOF3KgR0TfXoXgI=; b=Kvt5cDtfX41jr4 iNk5bcSaBlPORamLe3+Mpc88IzmhU5SE1ZynxYd+7CivuTJIm3XPbgJfzi68VxvLtVx0AEQj1KhnM Ao/9D7Mj7+hQXlu5qfkruBexmhu6WV3n9kz8rxpcioIL4tqS5F6S4041Z95ft5WbevCm0XYAHpsrM k2UKwyAIaw+KS1zuprBfPO2w8wBnB3ey22FJtm3RSad9CSZXgZqFumZxdi4ePvgTgm/p5ILtElCMe /mt3ZnRyR1G+PvGTw44hi6bxLtOpl+4LUSHSC1QGqjdr3Y9ZKZe5rFnSWntjEGJAMxvXRkFfiqYup jcStxlvAedm7fuB5WkdQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nhvhq-001HJo-G2; Fri, 22 Apr 2022 16:00:27 +0000 Received: from mail-co1nam11olkn20830.outbound.protection.outlook.com ([2a01:111:f400:7eab::830] helo=NAM11-CO1-obe.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nhveq-001GHT-8V for linux-arm-kernel@lists.infradead.org; Fri, 22 Apr 2022 15:57:22 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=H1FNmpN9DOyQo0575y/T2TyykMB4Z156FzWVeWwEcex+QpEmrgjduVmPL1obXuWrQF8P3RDC2Ep0X87TU6FgTI5uKWp2WCQJ65MdmKLc7nDjsUfDt9iGSLfFwPZyEmMTv39296y0+IyN1NYkYb9J/7gNGtRU1lFm8aHS1+JVY5ffznCd3PNkE8FkH0GEVVoDrPNA+PVzxJKAIk1FVagNiyeOLLCMKYMX13sm3zAPTF5aBjdwuXYSOtxk9ioSwCHOLU7ZsDzNFLkOTMIqQEnlW55gneNPB/zmddYsYlc85/BBTrglOazlmrfEXpvEluSBY6/cItTzcYBYyYNsr4B03g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=w214JjkWxts/kZdYSYyJbA2zAoSYiPb6tUrTOsI486A=; b=CF1PiUzUNMeQ9+ZqLMBf7/RVzk4t1jibhLnMqVhB2WMpEHsE+tjOcr6kP4vamGc0Hak4dESHnwoGq3pn0pEHnUP89Fo8Td2blgGOs+uFJ07kWCgIZSfCIQl5g9FAEZkwKz8QwgTrxqy3CHGUkEQcYgS4w+3r3nv/7rMudGRW1rVaVvnGVYAcSQsqkbCEu8mUJvaaeM016ugh8QNb8TMWV7Dw07A3uQapOtNEXzZ/HtpBydESlTBSQ5SpWKeVJ+Igqi0Zbk4VyOanNevruc4bfwTkbiXXwXQWDuF82jjBbMNKsNAc2HwrlBszNrnhGDXYPWwHiZor1GyHV9uCSa+Nyw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=none; dmarc=none; dkim=none; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=outlook.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=w214JjkWxts/kZdYSYyJbA2zAoSYiPb6tUrTOsI486A=; b=avIl6xb9ivtcLGSSB2c593ZJpAGneeVYLnxiVtHTcDy2915NSfu6Q6+9hsDVTetrt/0MemLtcSm6sJywl+6Khhz7Dt4TVkNJKN3k/HH4KMCZaNRx/PK55vcrXIUlyahFjobrA3ToDL1MuBVHdX+JHSWa986WYZ5z/ThjC1wxIgIJlTW4nZixhAyKYfKmZTQQuz9NKgnNXUtdaJiHMqqgWKJKxgYK8MdhXDkgg+31tLO2leBRBGUC0A0pNd8fkHxXDAAzBzdW9ZgH/boZPl2JjJep5Pjn9Dq25ngxNaMSTBZcfVOzvSLydO5sxstzRfdW4cJhJEsVEfBYNFn3kHEAZw== Received: from BYAPR20MB2472.namprd20.prod.outlook.com (2603:10b6:a03:155::16) by CY4PR2001MB0917.namprd20.prod.outlook.com (2603:10b6:903:d6::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5186.15; Fri, 22 Apr 2022 15:57:16 +0000 Received: from BYAPR20MB2472.namprd20.prod.outlook.com ([fe80::3480:160a:eb92:d6e3]) by BYAPR20MB2472.namprd20.prod.outlook.com ([fe80::3480:160a:eb92:d6e3%6]) with mapi id 15.20.5186.015; Fri, 22 Apr 2022 15:57:16 +0000 From: icenowy@outlook.com To: Mark Brown , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Maxime Ripard Cc: linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Icenowy Zheng Subject: [PATCH 3/4] spi: sun6i: add quirk for in-controller clock divider Date: Fri, 22 Apr 2022 23:56:38 +0800 Message-ID: X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220422155639.1071645-1-icenowy@outlook.com> References: <20220422155639.1071645-1-icenowy@outlook.com> X-TMN: [6on+UoLO1ATpsFxi0pyPJsItMb+i9p/A] X-ClientProxiedBy: HK0PR01CA0059.apcprd01.prod.exchangelabs.com (2603:1096:203:a6::23) To BYAPR20MB2472.namprd20.prod.outlook.com (2603:10b6:a03:155::16) X-Microsoft-Original-Message-ID: <20220422155639.1071645-4-icenowy@outlook.com> MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 27e00b0f-5279-4cf3-da4c-08da2478c62c X-MS-TrafficTypeDiagnostic: CY4PR2001MB0917:EE_ X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: dPKginjMP6LZfTjk1VtW8Pv4RLWarsXenZrYwgtH0SNDfyjwQptrmY2qopUzZ4W0i0drObBPzNaiSm9BdHYwDMhaArHpxPYSyXnO9qSpPYfYgMgjvzBBGtGWqKunBgGX42/2MyeFXdjYPQ26XWbWKJ3uXan7PXVGEChTr2PVezOJgUZFsG+KXiFt45IhIF1nSAsSp+CnO/ehpRHLm0528FccF+Hj2VAGkriXnChKbrbxoalRERv96Al7rR0fM1+FHK2rFqlH6kf3GWhEziFJwrIa6URe/DTgFRAU/V5b7R97+Boe8bZpq2GUfCaMMQde1r+PZO5cMrDD8mSr2c7U0sOmDAYvB574ZKzgNMXaexO4+6lF5nrLtB+XdHX8QGOjgwpvBXrrw8HGmCAefESrHY8cfN/0Dats/wwA48swne4ijiCQE5apZnsP6ckiqX/nqOo2YfzBCcnGeowhD3+rQiP8ON/bpLyOExM1Y0wVlnqghVzgv0bY0kAuJVmFeDu/rJomqoflMppijHIqA++IJxEmHg4gQGPffiVhhNNfcWxFI23/qkw5N7UTeNtP8YtWDIvpPokrtqDQa29COy5nqw== X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: P+vnShno19Ic9CduPeN6aaWaPDycWAQUGaRx9kLEovgbIyi57Iy91yGVizZCShxPzqNr2kS2ZLjkeH2BsA+dYzp3PEjsJcZdiuB0ihul5oKu75Mo2dOJe4Q7JwIQDTwbEOtFwDuCEbYiR8PSrHa+oZP5XTFWHMy0xRQ8Y7C+DxCWK+yxXxeCjUqKQxweytzLkzin+EdfxOpZKnrAvJrfR+QiUL2HHyv1pGOfjjHgPg/DVwW9Lp/xrU4bieQI2LwGwRGVOTR9xDgTON+14Ys/QWf1KzNz2JbipE0WvyjLVoisy27ToqGNfo/cNDQKtZ6DeKk3nYyDi3rC0gp4omhK6UmyPRpEbjN2s2SsGYWux3hbHk8Sk7WnLogZzMxgkZES13Q6I3rEMtmVW/nOa+K0Exg7oHJR20jPyigyfc4uuY4LMtDrRratGBA3cDgdAW976rvGfl5D9/H5PaR5x+9/UT+cqZdJ3ZN97aBqPCUVF8eBuQLFhX3Sy3/DjzQVdZx3nsg9Q705StiVbLUJ4psPkOTJMD9qtPqv30l2zc71oOrJTBW0sd4vu6ltbyKaLThqWW7wo5mqphOZMz8GPSXk/tREZjK3lT8Gv5z75+uldf60ZmHMfsqy6fJpB/Zq65ja7Xos1CshJNL2qs8SdYkbSMYhVMqXl4/zGIEGHSl8brWXHLUOEbyGd1Dugv+KxhX/929xYZFn6/OBBM2y6r2U+Xiqzl0QUMtfD0hU9/Eh7418vlEtGfMq6qIasKQAUsqDfLdKVSxV3TnKS3yrz71wPKEksMTQvPbWrIHhv8jBMuUN+9eYZVoFR0pMG0s4x4n9LLgjTXsYdKRdp0hyCV+ErKB06plL5LetQMuNuLMV14auzH6P3XTV+NjKJfV8OV460uABuagzsr0a1AM3GH1HW2VLRzoW6uAj7WVe+aH1f/qrWyfoKS+G+XhWmE9gyMhx30VnK4nDHKJxS3yoTHunFsEiZKwXLvxWb1qRyf0RKbZcuyHsSlRawb2YoaVaQQUsQmpuKjcvuuoElHw6H3BVOt5+dTSfcgvV8DFNrcWeaszpDrdrmXJKHhYISK1Hawb28eLA40Ry9eo/IhYzxumbHmV0ZvV44e8Y4Ib2KJfCM4ECQoe0ekYmolz+tUg6BhWhkAMebLV8vPC50ScNbd/N3gNKpyejFgjRwCsnu7uwj1yO1IvQoKZ5LrMGdo9If7YhAETkXuaDoybhA1ACU6RmprzsicvZ18LBPg7ED8XzHTkkUNBdfoB/hl/8UgPvwvZFOi4d35xbY43JycFRJL6T0aDYe5w8nFsi9cGaM0AUxQlnUSvEaWCcSWADsn0DIL4xTToEFcTrmnB1o3RQXvVTXfJPjtqV5aIIrWy9yFFcVfo5kIAiXGpCt9EhYK0Yv8Zkq/MUb+9/aOLFFJnhYwlbPrhF1KR+qY7BC8cwL3QgqmA= X-OriginatorOrg: outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 27e00b0f-5279-4cf3-da4c-08da2478c62c X-MS-Exchange-CrossTenant-AuthSource: BYAPR20MB2472.namprd20.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Apr 2022 15:57:16.8506 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 84df9e7f-e9f6-40af-b435-aaaaaaaaaaaa X-MS-Exchange-CrossTenant-RMS-PersistedConsumerOrg: 00000000-0000-0000-0000-000000000000 X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR2001MB0917 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220422_085720_379681_2FBF3282 X-CRM114-Status: GOOD ( 19.38 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Icenowy Zheng Previously SPI controllers in Allwinner SoCs has a clock divider inside. However now the clock divider is removed and to set the transfer clock rate it's only needed to set the SPI module clock to the target value. Add a quirk for this kind of SPI controllers. Signed-off-by: Icenowy Zheng --- drivers/spi/spi-sun6i.c | 68 +++++++++++++++++++++++------------------ 1 file changed, 38 insertions(+), 30 deletions(-) diff --git a/drivers/spi/spi-sun6i.c b/drivers/spi/spi-sun6i.c index 84c525b08ad0..fc81afc3a963 100644 --- a/drivers/spi/spi-sun6i.c +++ b/drivers/spi/spi-sun6i.c @@ -87,6 +87,7 @@ struct sun6i_spi_cfg { unsigned long fifo_depth; + bool has_clk_ctl; }; struct sun6i_spi { @@ -260,7 +261,7 @@ static int sun6i_spi_transfer_one(struct spi_master *master, struct spi_transfer *tfr) { struct sun6i_spi *sspi = spi_master_get_devdata(master); - unsigned int mclk_rate, div, div_cdr1, div_cdr2, timeout; + unsigned int div, div_cdr1, div_cdr2, timeout; unsigned int start, end, tx_time; unsigned int trig_level; unsigned int tx_len = 0, rx_len = 0; @@ -350,39 +351,44 @@ static int sun6i_spi_transfer_one(struct spi_master *master, sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg); - /* Ensure that we have a parent clock fast enough */ - mclk_rate = clk_get_rate(sspi->mclk); - if (mclk_rate < (2 * tfr->speed_hz)) { - clk_set_rate(sspi->mclk, 2 * tfr->speed_hz); - mclk_rate = clk_get_rate(sspi->mclk); - } + if (sspi->cfg->has_clk_ctl) { + unsigned int mclk_rate = clk_get_rate(sspi->mclk); + /* Ensure that we have a parent clock fast enough */ + if (mclk_rate < (2 * tfr->speed_hz)) { + clk_set_rate(sspi->mclk, 2 * tfr->speed_hz); + mclk_rate = clk_get_rate(sspi->mclk); + } - /* - * Setup clock divider. - * - * We have two choices there. Either we can use the clock - * divide rate 1, which is calculated thanks to this formula: - * SPI_CLK = MOD_CLK / (2 ^ cdr) - * Or we can use CDR2, which is calculated with the formula: - * SPI_CLK = MOD_CLK / (2 * (cdr + 1)) - * Wether we use the former or the latter is set through the - * DRS bit. - * - * First try CDR2, and if we can't reach the expected - * frequency, fall back to CDR1. - */ - div_cdr1 = DIV_ROUND_UP(mclk_rate, tfr->speed_hz); - div_cdr2 = DIV_ROUND_UP(div_cdr1, 2); - if (div_cdr2 <= (SUN6I_CLK_CTL_CDR2_MASK + 1)) { - reg = SUN6I_CLK_CTL_CDR2(div_cdr2 - 1) | SUN6I_CLK_CTL_DRS; - tfr->effective_speed_hz = mclk_rate / (2 * div_cdr2); + /* + * Setup clock divider. + * + * We have two choices there. Either we can use the clock + * divide rate 1, which is calculated thanks to this formula: + * SPI_CLK = MOD_CLK / (2 ^ cdr) + * Or we can use CDR2, which is calculated with the formula: + * SPI_CLK = MOD_CLK / (2 * (cdr + 1)) + * Wether we use the former or the latter is set through the + * DRS bit. + * + * First try CDR2, and if we can't reach the expected + * frequency, fall back to CDR1. + */ + div_cdr1 = DIV_ROUND_UP(mclk_rate, tfr->speed_hz); + div_cdr2 = DIV_ROUND_UP(div_cdr1, 2); + if (div_cdr2 <= (SUN6I_CLK_CTL_CDR2_MASK + 1)) { + reg = SUN6I_CLK_CTL_CDR2(div_cdr2 - 1) | SUN6I_CLK_CTL_DRS; + tfr->effective_speed_hz = mclk_rate / (2 * div_cdr2); + } else { + div = min(SUN6I_CLK_CTL_CDR1_MASK, order_base_2(div_cdr1)); + reg = SUN6I_CLK_CTL_CDR1(div); + tfr->effective_speed_hz = mclk_rate / (1 << div); + } + + sun6i_spi_write(sspi, SUN6I_CLK_CTL_REG, reg); } else { - div = min(SUN6I_CLK_CTL_CDR1_MASK, order_base_2(div_cdr1)); - reg = SUN6I_CLK_CTL_CDR1(div); - tfr->effective_speed_hz = mclk_rate / (1 << div); + clk_set_rate(sspi->mclk, tfr->speed_hz); } - sun6i_spi_write(sspi, SUN6I_CLK_CTL_REG, reg); /* Finally enable the bus - doing so before might raise SCK to HIGH */ reg = sun6i_spi_read(sspi, SUN6I_GBL_CTL_REG); reg |= SUN6I_GBL_CTL_BUS_ENABLE; @@ -702,10 +708,12 @@ static int sun6i_spi_remove(struct platform_device *pdev) static const struct sun6i_spi_cfg sun6i_a31_spi_cfg = { .fifo_depth = SUN6I_FIFO_DEPTH, + .has_clk_ctl = true, }; static const struct sun6i_spi_cfg sun8i_h3_spi_cfg = { .fifo_depth = SUN8I_FIFO_DEPTH, + .has_clk_ctl = true, }; static const struct of_device_id sun6i_spi_match[] = {