From patchwork Thu Sep 20 09:58:53 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Catalin Marinas X-Patchwork-Id: 1483551 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id 934483FD40 for ; Thu, 20 Sep 2012 10:01:24 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TEdXR-0001Kw-Em; Thu, 20 Sep 2012 09:59:17 +0000 Received: from mail-qc0-f177.google.com ([209.85.216.177]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1TEdXP-0001KY-0m for linux-arm-kernel@lists.infradead.org; Thu, 20 Sep 2012 09:59:15 +0000 Received: by qcsu28 with SMTP id u28so1666761qcs.36 for ; Thu, 20 Sep 2012 02:59:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:sender:in-reply-to:references:from:date :x-google-sender-auth:message-id:subject:to:cc:content-type; bh=RGrCPEemo1p141Nsz/93KiL5iCOzM+hKFQO8gSK2AEg=; b=rpNFtksOnZgDyfzzIL5UztJCl7i/Z5u2O2EzJIXIT0oeJBcJb5uFZu3Dnqfftw3nI+ FPijISbyRjQnmNJ0kfHl0agVGXEakZwhBgH4/QJZpQXS+txEdlxxiBMsIoz7E6AEvAhT bvYr1Zj1hB3vTR8XWejeGz6w1J1a3EXX0PQ3Kh/b1FEmytQ/2UpUBwpDDAD1sgzGXWQy NZUTr6125lGx0Zx7GNoQWLNjgfDQeEut/YUhPrAYTSOw1aZr+Iqak6bYRtPEs4pY3ooh QatzOpchMoq0Oz0X4chfXw/fGBYotJthPyUngO+yERq3s1zhZK1aW1qR8njDk9TQqmTx V+yQ== Received: by 10.224.193.69 with SMTP id dt5mr3230641qab.2.1348135154202; Thu, 20 Sep 2012 02:59:14 -0700 (PDT) MIME-Version: 1.0 Received: by 10.49.103.135 with HTTP; Thu, 20 Sep 2012 02:58:53 -0700 (PDT) In-Reply-To: <1347434097-7924-2-git-send-email-horms@verge.net.au> References: <1347434097-7924-1-git-send-email-horms@verge.net.au> <1347434097-7924-2-git-send-email-horms@verge.net.au> From: Catalin Marinas Date: Thu, 20 Sep 2012 10:58:53 +0100 X-Google-Sender-Auth: B4mkRcv1h48CAJ9H1bs_yPCp254 Message-ID: Subject: Re: [PATCH 1/2] arm: Add ARM ERRATA 775420 workaround To: Simon Horman X-Spam-Note: CRM114 invocation failed X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.216.177 listed in list.dnswl.org] 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (catalin.marinas[at]gmail.com) -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature Cc: Paul Mundt , Magnus Damm , linux-arm-kernel@lists.infradead.org, Russell King , linux-sh@vger.kernel.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org On 12 September 2012 08:14, Simon Horman wrote: > +config ARM_ERRATA_775420 > + bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" > + depends on CPU_V7 > + help > + This option enables the workaround for the 775420 Cortex-A9 (r2p2, > + r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance > + operation aborts with MMU exception, it might cause the processor > + deadlock. This workaround puts DSB before executing ISB at the > + beginning of the abort exception handler. > + > endmenu The only case where we can get an abort on cache maintenance is v7_coherent_user_range(). I don't think we have any ISB on the exception handling path for this function, so we could just add the DSB there: --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S @@ -211,6 +211,9 @@ ENTRY(v7_coherent_user_range) * isn't mapped, fail with -EFAULT. */ 9001: +#ifdef CONFIG_ARM_ERRATA_775420 + dsb +#endif mov r0, #-EFAULT mov pc, lr UNWIND(.fnend )