| Message ID | CAHrpEqT_34eNK-EzRgs-ocDD6pfLzD=FU8n83HgSQVsimJRxPw@mail.gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | None | expand |
On Wed, Jun 19, 2019 at 01:46:00PM -0500, Zhi Li wrote: > Add ddr performance monitor > > Signed-off-by: Frank Li <Frank.Li@nxp.com> > Reviewed-by: Fabio Estevam <festevam@gmail.com> > --- > > Resent without base64 encode > > Notes: > No change from v9 to v12 > > Change from v8 to v9 > * put ddr-pmu under ddr_subsystem bus > > Change from v3 to v8 > * none > > Change from v2 to v3 > * ddr_pmu0 -> ddr-pmu > > arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi > b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi > index 0683ee2..a33e08c 100644 > --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi > @@ -378,6 +378,20 @@ > }; > }; > > + ddr_subsyss: bus@5c000000 { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x5c000000 0x0 0x5c000000 0x1000000>; > + > + ddr-pmu@5c020000 { > + compatible = "fsl,imx8-ddr-pmu"; > + reg = <0x5c020000 0x10000>; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; > + }; > + }; > + > lsio_subsys: bus@5d000000 { > compatible = "simple-bus"; > #address-cells = <1>; The patch format is corrupted. All tabs are turned into spaces here. I manually apply the patch, but please avoid it next time. Shawn > -- > 2.5.2
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi index 0683ee2..a33e08c 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi @@ -378,6 +378,20 @@ }; }; + ddr_subsyss: bus@5c000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x5c000000 0x0 0x5c000000 0x1000000>; + + ddr-pmu@5c020000 { + compatible = "fsl,imx8-ddr-pmu"; + reg = <0x5c020000 0x10000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + lsio_subsys: bus@5d000000 { compatible = "simple-bus"; #address-cells = <1>;