[15/75] ARM: l2c: add and use L2C revision constants

Message ID	E1WTYVM-0005Ze-IW@rmk-PC.arm.linux.org.uk (mailing list archive)
State	New, archived
Headers	show Return-Path: <linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org> In-Reply-To: <20140328151249.GJ7528@n2100.arm.linux.org.uk> References: <20140328151249.GJ7528@n2100.arm.linux.org.uk> From: Russell King <rmk+kernel@arm.linux.org.uk> To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 15/75] ARM: l2c: add and use L2C revision constants Message-Id: <E1WTYVM-0005Ze-IW@rmk-PC.arm.linux.org.uk> Date: Fri, 28 Mar 2014 15:15:36 +0000 Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" <linux-arm-kernel-bounces@lists.infradead.org> Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org

Message ID

E1WTYVM-0005Ze-IW@rmk-PC.arm.linux.org.uk (mailing list archive)

State

New, archived

Headers

In-Reply-To: <20140328151249.GJ7528@n2100.arm.linux.org.uk>
References: <20140328151249.GJ7528@n2100.arm.linux.org.uk>
From: Russell King <rmk+kernel@arm.linux.org.uk>
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 15/75] ARM: l2c: add and use L2C revision constants
Message-Id: <E1WTYVM-0005Ze-IW@rmk-PC.arm.linux.org.uk>
Date: Fri, 28 Mar 2014 15:15:36 +0000
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MIME-Version: 1.0
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Commit Message

Russell King March 28, 2014, 3:15 p.m. UTC

The revision namespace is specific to the L2 cache part, so don't name
these with generic identifiers, use a part specific identifier.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/include/asm/hardware/cache-l2x0.h | 22 ++++++++++++++++------
 arch/arm/mm/cache-l2x0.c                   | 10 +++++-----
 2 files changed, 21 insertions(+), 11 deletions(-)

Comments

Michal Simek April 2, 2014, 9:37 a.m. UTC | #1

On 03/28/2014 04:15 PM, Russell King wrote:
> The revision namespace is specific to the L2 cache part, so don't name
> these with generic identifiers, use a part specific identifier.
> 
> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
> ---
>  arch/arm/include/asm/hardware/cache-l2x0.h | 22 ++++++++++++++++------
>  arch/arm/mm/cache-l2x0.c                   | 10 +++++-----
>  2 files changed, 21 insertions(+), 11 deletions(-)
> 
> diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h
> index 6795ff743b3d..94fbcec216ae 100644
> --- a/arch/arm/include/asm/hardware/cache-l2x0.h
> +++ b/arch/arm/include/asm/hardware/cache-l2x0.h
> @@ -68,14 +68,24 @@
>  /* Registers shifts and masks */
>  #define L2X0_CACHE_ID_PART_MASK		(0xf << 6)
>  #define L2X0_CACHE_ID_PART_L210		(1 << 6)
> +#define L2X0_CACHE_ID_PART_L220		(2 << 6)
>  #define L2X0_CACHE_ID_PART_L310		(3 << 6)
>  #define L2X0_CACHE_ID_RTL_MASK          0x3f
> -#define L2X0_CACHE_ID_RTL_R0P0          0x0
> -#define L2X0_CACHE_ID_RTL_R1P0          0x2
> -#define L2X0_CACHE_ID_RTL_R2P0          0x4
> -#define L2X0_CACHE_ID_RTL_R3P0          0x5
> -#define L2X0_CACHE_ID_RTL_R3P1          0x6
> -#define L2X0_CACHE_ID_RTL_R3P2          0x8
> +#define L210_CACHE_ID_RTL_R0P2_02	0x00
> +#define L210_CACHE_ID_RTL_R0P1		0x01
> +#define L210_CACHE_ID_RTL_R0P2_01	0x02
> +#define L210_CACHE_ID_RTL_R0P3		0x03
> +#define L210_CACHE_ID_RTL_R0P4		0x0b
> +#define L210_CACHE_ID_RTL_R0P5		0x0f
> +#define L220_CACHE_ID_RTL_R1P7_01REL0	0x06
> +#define L310_CACHE_ID_RTL_R0P0          0x00
> +#define L310_CACHE_ID_RTL_R1P0          0x02
> +#define L310_CACHE_ID_RTL_R2P0          0x04
> +#define L310_CACHE_ID_RTL_R3P0          0x05
> +#define L310_CACHE_ID_RTL_R3P1          0x06
> +#define L310_CACHE_ID_RTL_R3P1_50REL0	0x07
> +#define L310_CACHE_ID_RTL_R3P2          0x08
> +#define L310_CACHE_ID_RTL_R3P3		0x09

Will be good to also clear tabs and spaces usage here
(tabs or spaces not mixing both).

Thanks,
Michal

Russell King - ARM Linux April 3, 2014, 7:06 p.m. UTC | #2

On Wed, Apr 02, 2014 at 11:37:34AM +0200, Michal Simek wrote:
> On 03/28/2014 04:15 PM, Russell King wrote:
> > The revision namespace is specific to the L2 cache part, so don't name
> > these with generic identifiers, use a part specific identifier.
> > 
> > Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
> > ---
> >  arch/arm/include/asm/hardware/cache-l2x0.h | 22 ++++++++++++++++------
> >  arch/arm/mm/cache-l2x0.c                   | 10 +++++-----
> >  2 files changed, 21 insertions(+), 11 deletions(-)
> > 
> > diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h
> > index 6795ff743b3d..94fbcec216ae 100644
> > --- a/arch/arm/include/asm/hardware/cache-l2x0.h
> > +++ b/arch/arm/include/asm/hardware/cache-l2x0.h
> > @@ -68,14 +68,24 @@
> >  /* Registers shifts and masks */
> >  #define L2X0_CACHE_ID_PART_MASK		(0xf << 6)
> >  #define L2X0_CACHE_ID_PART_L210		(1 << 6)
> > +#define L2X0_CACHE_ID_PART_L220		(2 << 6)
> >  #define L2X0_CACHE_ID_PART_L310		(3 << 6)
> >  #define L2X0_CACHE_ID_RTL_MASK          0x3f
> > -#define L2X0_CACHE_ID_RTL_R0P0          0x0
> > -#define L2X0_CACHE_ID_RTL_R1P0          0x2
> > -#define L2X0_CACHE_ID_RTL_R2P0          0x4
> > -#define L2X0_CACHE_ID_RTL_R3P0          0x5
> > -#define L2X0_CACHE_ID_RTL_R3P1          0x6
> > -#define L2X0_CACHE_ID_RTL_R3P2          0x8
> > +#define L210_CACHE_ID_RTL_R0P2_02	0x00
> > +#define L210_CACHE_ID_RTL_R0P1		0x01
> > +#define L210_CACHE_ID_RTL_R0P2_01	0x02
> > +#define L210_CACHE_ID_RTL_R0P3		0x03
> > +#define L210_CACHE_ID_RTL_R0P4		0x0b
> > +#define L210_CACHE_ID_RTL_R0P5		0x0f
> > +#define L220_CACHE_ID_RTL_R1P7_01REL0	0x06
> > +#define L310_CACHE_ID_RTL_R0P0          0x00
> > +#define L310_CACHE_ID_RTL_R1P0          0x02
> > +#define L310_CACHE_ID_RTL_R2P0          0x04
> > +#define L310_CACHE_ID_RTL_R3P0          0x05
> > +#define L310_CACHE_ID_RTL_R3P1          0x06
> > +#define L310_CACHE_ID_RTL_R3P1_50REL0	0x07
> > +#define L310_CACHE_ID_RTL_R3P2          0x08
> > +#define L310_CACHE_ID_RTL_R3P3		0x09
> 
> Will be good to also clear tabs and spaces usage here
> (tabs or spaces not mixing both).

That's because I just modified the names of the old ones, and added the
new ones using tabs.  All +'d lines fixed to use tabs.  I haven't changed
the L2X0_CACHE_ID_RTL_MASK line because that would imply I'm doing a
cleanup to this rather than fixing these definitions.

diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h
index 6795ff743b3d..94fbcec216ae 100644
--- a/arch/arm/include/asm/hardware/cache-l2x0.h
+++ b/arch/arm/include/asm/hardware/cache-l2x0.h
@@ -68,14 +68,24 @@ 
 /* Registers shifts and masks */
 #define L2X0_CACHE_ID_PART_MASK		(0xf << 6)
 #define L2X0_CACHE_ID_PART_L210		(1 << 6)
+#define L2X0_CACHE_ID_PART_L220		(2 << 6)
 #define L2X0_CACHE_ID_PART_L310		(3 << 6)
 #define L2X0_CACHE_ID_RTL_MASK          0x3f
-#define L2X0_CACHE_ID_RTL_R0P0          0x0
-#define L2X0_CACHE_ID_RTL_R1P0          0x2
-#define L2X0_CACHE_ID_RTL_R2P0          0x4
-#define L2X0_CACHE_ID_RTL_R3P0          0x5
-#define L2X0_CACHE_ID_RTL_R3P1          0x6
-#define L2X0_CACHE_ID_RTL_R3P2          0x8
+#define L210_CACHE_ID_RTL_R0P2_02	0x00
+#define L210_CACHE_ID_RTL_R0P1		0x01
+#define L210_CACHE_ID_RTL_R0P2_01	0x02
+#define L210_CACHE_ID_RTL_R0P3		0x03
+#define L210_CACHE_ID_RTL_R0P4		0x0b
+#define L210_CACHE_ID_RTL_R0P5		0x0f
+#define L220_CACHE_ID_RTL_R1P7_01REL0	0x06
+#define L310_CACHE_ID_RTL_R0P0          0x00
+#define L310_CACHE_ID_RTL_R1P0          0x02
+#define L310_CACHE_ID_RTL_R2P0          0x04
+#define L310_CACHE_ID_RTL_R3P0          0x05
+#define L310_CACHE_ID_RTL_R3P1          0x06
+#define L310_CACHE_ID_RTL_R3P1_50REL0	0x07
+#define L310_CACHE_ID_RTL_R3P2          0x08
+#define L310_CACHE_ID_RTL_R3P3		0x09
 
 #define L2X0_AUX_CTRL_MASK			0xc0000fff
 #define L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT	0
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 29ee7f692801..c39602ef2cdd 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -374,7 +374,7 @@  void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
 		/* Unmapped register. */
 		sync_reg_offset = L2X0_DUMMY_REG;
 #endif
-		if ((cache_id & L2X0_CACHE_ID_RTL_MASK) <= L2X0_CACHE_ID_RTL_R3P0)
+		if ((cache_id & L2X0_CACHE_ID_RTL_MASK) <= L310_CACHE_ID_RTL_R3P0)
 			outer_cache.set_debug = pl310_set_debug;
 		break;
 	case L2X0_CACHE_ID_PART_L210:
@@ -768,7 +768,7 @@  static void __init pl310_save(void)
 	l2x0_saved_regs.filter_start = readl_relaxed(l2x0_base +
 		L2X0_ADDR_FILTER_START);
 
-	if (l2x0_revision >= L2X0_CACHE_ID_RTL_R2P0) {
+	if (l2x0_revision >= L310_CACHE_ID_RTL_R2P0) {
 		/*
 		 * From r2p0, there is Prefetch offset/control register
 		 */
@@ -777,7 +777,7 @@  static void __init pl310_save(void)
 		/*
 		 * From r3p0, there is Power control register
 		 */
-		if (l2x0_revision >= L2X0_CACHE_ID_RTL_R3P0)
+		if (l2x0_revision >= L310_CACHE_ID_RTL_R3P0)
 			l2x0_saved_regs.pwr_ctrl = readl_relaxed(l2x0_base +
 				L2X0_POWER_CTRL);
 	}
@@ -830,10 +830,10 @@  static void pl310_resume(void)
 		l2x0_revision = readl_relaxed(l2x0_base + L2X0_CACHE_ID) &
 			L2X0_CACHE_ID_RTL_MASK;
 
-		if (l2x0_revision >= L2X0_CACHE_ID_RTL_R2P0) {
+		if (l2x0_revision >= L310_CACHE_ID_RTL_R2P0) {
 			writel_relaxed(l2x0_saved_regs.prefetch_ctrl,
 				l2x0_base + L2X0_PREFETCH_CTRL);
-			if (l2x0_revision >= L2X0_CACHE_ID_RTL_R3P0)
+			if (l2x0_revision >= L310_CACHE_ID_RTL_R3P0)
 				writel_relaxed(l2x0_saved_regs.pwr_ctrl,
 					l2x0_base + L2X0_POWER_CTRL);
 		}

[15/75] ARM: l2c: add and use L2C revision constants

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