From patchwork Wed Jun 28 19:25:59 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 9815267 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 707A3603F2 for ; Wed, 28 Jun 2017 19:42:43 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5F1DD28066 for ; Wed, 28 Jun 2017 19:42:43 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 53CCA28574; Wed, 28 Jun 2017 19:42:43 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id C61A028575 for ; Wed, 28 Jun 2017 19:42:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:Subject:Date: Message-Id:In-Reply-To:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: References:List-Owner; bh=WMVZ42HH3NR+X/baR2kwgog3/6MPZZggQcJpnbdKK4o=; b=HFS QGPJEaCnFhoDFmm8qnvvrJ+xl4oF/0y9Da0f80rLIwVKDAgyLsTfuP7RpU4p/4usPPrPbWFmwMYzd gbRsepHudgxiQ8z5oBvjeKxQDjKkuKpImZaL1qB7OE4ITflcVgnc7DYq3mecv52p62xivRaDHBYG/ +5JdrSKFoUyJIHh4pSyWvpzQXfuz6ww64Mw5Voe+X0Rtc1/quaVcXmfzQHO7jxh84rYf8oMtc73c9 c8Lz8ZfhBWiXGo1EyXNWCROlX4yvWXqR5jpOjLP34/Y884479YIR26JwxoQ/Fl+bjnGoJLN/ja0pI 1uii/kxRWf9BJ3miESZS7DEv1XnTQiA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1dQIrH-0007SR-6S; Wed, 28 Jun 2017 19:42:39 +0000 Received: from casper.infradead.org ([2001:8b0:10b:1236::1]) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1dQIpx-0005JH-BD; Wed, 28 Jun 2017 19:41:17 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=casper.20170209; h=Subject:Date:Message-Id:In-Reply-To:Cc: To:From:Sender:Reply-To:MIME-Version:Content-Type:Content-Transfer-Encoding: Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID:References:List-Id:List-Help: List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=vmxR6EmbVfkwn5ulQsK3UEBl0f8WXcLT3eIdNvkos3s=; b=rQfJQkr7A7iffaNSMn5vZdDm+W MihkH8o+2wsDyfExv6wIZkBBJ0nvGuudlw8z4Z9SBHWXFha+F3cisCDvp1ifdAtsbqa0s91PwuODc 37LsPvwUbXufhBMc3kokbhVzHshnX8JTEt00D3NmX9ZBt/r+bpsmBJgtuCMq2IB3cRLRb70w4my2z zljHKhIlixFhgbrJRoFbIMD08EnxnpmiR4/dlzYreCjeBBv+t1T+JwomCNvV2eevITHknJOIIXmbZ 9elyMEAcij1LyjvtaOrVOF+1dRIkm8Wj8HKdG+JB8SJL9KtnXhUAthfTU802jX/1HPvKU3bxVpQpm RuBRsHhg==; Received: from mezzanine.sirena.org.uk ([2400:8900::f03c:91ff:fedb:4f4]) by casper.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1dQIbw-0003Wz-Jg; Wed, 28 Jun 2017 19:26:50 +0000 Received: from [176.12.107.140] (helo=finisterre) by mezzanine.sirena.org.uk with esmtpsa (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.89) (envelope-from ) id 1dQIbD-0001bU-7D; Wed, 28 Jun 2017 19:26:05 +0000 Received: from broonie by finisterre with local (Exim 4.89) (envelope-from ) id 1dQIb9-0004iH-1G; Wed, 28 Jun 2017 20:25:59 +0100 From: Mark Brown To: Jeffy Chen In-Reply-To: <1498624723-17332-2-git-send-email-jeffy.chen@rock-chips.com> Message-Id: Date: Wed, 28 Jun 2017 20:25:59 +0100 X-SA-Exim-Connect-IP: 176.12.107.140 X-SA-Exim-Mail-From: broonie@sirena.org.uk Subject: Applied "spi: rockchip: Disable Runtime PM when chip select is asserted" to the spi tree X-SA-Exim-Version: 4.2.1 (built Tue, 02 Aug 2016 21:08:31 +0000) X-SA-Exim-Scanned: No (on mezzanine.sirena.org.uk); Unknown failure X-Bad-Reply: In-Reply-To but no 'Re:' in Subject. X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170628_202648_889108_703DA135 X-CRM114-Status: GOOD ( 21.77 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dianders@chromium.org, heiko@sntech.de, briannorris@chromium.org, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org, linux-rockchip@lists.infradead.org, broonie@kernel.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The patch spi: rockchip: Disable Runtime PM when chip select is asserted has been applied to the spi tree at git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. Thanks, Mark From aa099382ac0cda27e10fa8f45bf91edea0d1d35e Mon Sep 17 00:00:00 2001 From: Jeffy Chen Date: Wed, 28 Jun 2017 12:38:43 +0800 Subject: [PATCH] spi: rockchip: Disable Runtime PM when chip select is asserted The rockchip spi would stop driving pins when runtime suspended, which might break slave's xfer(for example cros_ec). Since we have pullups on those pins, we only need to care about this when the CS asserted. So let's keep the spi alive when chip select is asserted. Also use pm_runtime_put instead of pm_runtime_put_sync. Suggested-by: Doug Anderson Signed-off-by: Jeffy Chen Reviewed-by: Douglas Anderson Signed-off-by: Mark Brown --- drivers/spi/spi-rockchip.c | 51 +++++++++++++++++++++++----------------------- 1 file changed, 26 insertions(+), 25 deletions(-) diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c index 52ea1605d4c6..0b4a52b3e1dc 100644 --- a/drivers/spi/spi-rockchip.c +++ b/drivers/spi/spi-rockchip.c @@ -25,6 +25,11 @@ #define DRIVER_NAME "rockchip-spi" +#define ROCKCHIP_SPI_CLR_BITS(reg, bits) \ + writel_relaxed(readl_relaxed(reg) & ~(bits), reg) +#define ROCKCHIP_SPI_SET_BITS(reg, bits) \ + writel_relaxed(readl_relaxed(reg) | (bits), reg) + /* SPI register offsets */ #define ROCKCHIP_SPI_CTRLR0 0x0000 #define ROCKCHIP_SPI_CTRLR1 0x0004 @@ -149,6 +154,8 @@ */ #define ROCKCHIP_SPI_MAX_TRANLEN 0xffff +#define ROCKCHIP_SPI_MAX_CS_NUM 2 + enum rockchip_ssi_type { SSI_MOTO_SPI = 0, SSI_TI_SSP, @@ -193,6 +200,8 @@ struct rockchip_spi { /* protect state */ spinlock_t lock; + bool cs_asserted[ROCKCHIP_SPI_MAX_CS_NUM]; + u32 use_dma; struct sg_table tx_sg; struct sg_table rx_sg; @@ -264,37 +273,29 @@ static inline u32 rx_max(struct rockchip_spi *rs) static void rockchip_spi_set_cs(struct spi_device *spi, bool enable) { - u32 ser; struct spi_master *master = spi->master; struct rockchip_spi *rs = spi_master_get_devdata(master); + bool cs_asserted = !enable; - pm_runtime_get_sync(rs->dev); + /* Return immediately for no-op */ + if (cs_asserted == rs->cs_asserted[spi->chip_select]) + return; - ser = readl_relaxed(rs->regs + ROCKCHIP_SPI_SER) & SER_MASK; + if (cs_asserted) { + /* Keep things powered as long as CS is asserted */ + pm_runtime_get_sync(rs->dev); - /* - * drivers/spi/spi.c: - * static void spi_set_cs(struct spi_device *spi, bool enable) - * { - * if (spi->mode & SPI_CS_HIGH) - * enable = !enable; - * - * if (spi->cs_gpio >= 0) - * gpio_set_value(spi->cs_gpio, !enable); - * else if (spi->master->set_cs) - * spi->master->set_cs(spi, !enable); - * } - * - * Note: enable(rockchip_spi_set_cs) = !enable(spi_set_cs) - */ - if (!enable) - ser |= 1 << spi->chip_select; - else - ser &= ~(1 << spi->chip_select); + ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER, + BIT(spi->chip_select)); + } else { + ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER, + BIT(spi->chip_select)); - writel_relaxed(ser, rs->regs + ROCKCHIP_SPI_SER); + /* Drop reference from when we first asserted CS */ + pm_runtime_put(rs->dev); + } - pm_runtime_put_sync(rs->dev); + rs->cs_asserted[spi->chip_select] = cs_asserted; } static int rockchip_spi_prepare_message(struct spi_master *master, @@ -739,7 +740,7 @@ static int rockchip_spi_probe(struct platform_device *pdev) master->auto_runtime_pm = true; master->bus_num = pdev->id; master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP; - master->num_chipselect = 2; + master->num_chipselect = ROCKCHIP_SPI_MAX_CS_NUM; master->dev.of_node = pdev->dev.of_node; master->bits_per_word_mask = SPI_BPW_MASK(16) | SPI_BPW_MASK(8);