| Message ID | MN2PR08MB579006CB67AC63A93C8B0D5E89760@MN2PR08MB5790.namprd08.prod.outlook.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v2] clk: sunxi-ng: v3s: Fix incorrect number of hw_clks. | expand |
Hi, On Wed, Nov 13, 2019 at 09:23:59AM +0000, Tian Yunhao wrote: > The hws field of sun8i_v3s_hw_clks has only 74 > members. However, the number specified by CLK_NUMBER > is 77 (= CLK_I2S0 + 1). This leads to runtime segmentation > fault that is not always reproducible. > > This patch corrects this behavior by separating clock > numbers for V3 and V3S. > > Signed-off-by: Yunhao Tian <t123yh@outlook.com> Even though they are similar, the Signed-off-by doesn't match the authorship. > --- > drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 4 ++-- > drivers/clk/sunxi-ng/ccu-sun8i-v3s.h | 3 ++- > 2 files changed, 4 insertions(+), 3 deletions(-) > > diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c > index 5c779eec454b..72a87dd0c0d8 100644 > --- a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c > +++ b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c > @@ -618,7 +618,7 @@ static struct clk_hw_onecell_data sun8i_v3s_hw_clks = { > [CLK_MBUS] = &mbus_clk.common.hw, > [CLK_MIPI_CSI] = &mipi_csi_clk.common.hw, > }, > - .num = CLK_NUMBER, > + .num = CLK_NUMBER_V3S, > }; > > static struct clk_hw_onecell_data sun8i_v3_hw_clks = { > @@ -700,7 +700,7 @@ static struct clk_hw_onecell_data sun8i_v3_hw_clks = { > [CLK_MBUS] = &mbus_clk.common.hw, > [CLK_MIPI_CSI] = &mipi_csi_clk.common.hw, > }, > - .num = CLK_NUMBER, > + .num = CLK_NUMBER_V3, There's not much point in having a defined CLK_NUMBER here, just use the value you've defined it to (so CLK_I2S0 + 1 and CLK_PLL_DDR1 + 1) Maxime
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c index 5c779eec454b..72a87dd0c0d8 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c @@ -618,7 +618,7 @@ static struct clk_hw_onecell_data sun8i_v3s_hw_clks = { [CLK_MBUS] = &mbus_clk.common.hw, [CLK_MIPI_CSI] = &mipi_csi_clk.common.hw, }, - .num = CLK_NUMBER, + .num = CLK_NUMBER_V3S, }; static struct clk_hw_onecell_data sun8i_v3_hw_clks = { @@ -700,7 +700,7 @@ static struct clk_hw_onecell_data sun8i_v3_hw_clks = { [CLK_MBUS] = &mbus_clk.common.hw, [CLK_MIPI_CSI] = &mipi_csi_clk.common.hw, }, - .num = CLK_NUMBER, + .num = CLK_NUMBER_V3, }; static struct ccu_reset_map sun8i_v3s_ccu_resets[] = { diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.h b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.h index b0160d305a67..18cf8f3c112b 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.h +++ b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.h @@ -51,6 +51,7 @@ #define CLK_PLL_DDR1 74 -#define CLK_NUMBER (CLK_I2S0 + 1) +#define CLK_NUMBER_V3 (CLK_I2S0 + 1) +#define CLK_NUMBER_V3S (CLK_PLL_DDR1 + 1) #endif /* _CCU_SUN8I_H3_H_ */
The hws field of sun8i_v3s_hw_clks has only 74 members. However, the number specified by CLK_NUMBER is 77 (= CLK_I2S0 + 1). This leads to runtime segmentation fault that is not always reproducible. This patch corrects this behavior by separating clock numbers for V3 and V3S. Signed-off-by: Yunhao Tian <t123yh@outlook.com> --- drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 4 ++-- drivers/clk/sunxi-ng/ccu-sun8i-v3s.h | 3 ++- 2 files changed, 4 insertions(+), 3 deletions(-)