From patchwork Tue Nov 8 03:16:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Torokhov X-Patchwork-Id: 13035752 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4AD94C4332F for ; Tue, 8 Nov 2022 03:18:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Subject:Cc:To: From:Date:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=S5zKciObiVxlSzyeofLj9uipOqNBqTgN/G/Ya2jpRwM=; b=nQBqSj1eVE1nR1 geRu9QLrUTiRXivq8gZzTpB/GlrhicT0drvmgQc+mz5zpS3hQM1LTl4vtWCm8TrNf6xAA/lx8ZAGa VsSe0b1aiN6Edtz2huaCmiFa/PK6PMk6F8RNpfNhOhDXBQzAf3ZXY3TW5BdaNSuV5vR42l+8ZM5CF YreEVoOD1sbsGKWaIq4BZZF/loT3X6BhzwIyi29hWWi1SP9RkjBPs3y9OLNUgMqS2de9TYwnnCth7 s3SClBuqsjvCO6Yt2f8Pk6YNzVwudaztz1Tz9dL7Na+MZArYVzyI8K/upiC4j16DQ1y1hs1+sB/2K +u7cJ7BJUopnXhASlPoQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1osF6g-002I39-Se; Tue, 08 Nov 2022 03:16:58 +0000 Received: from mail-pj1-x1036.google.com ([2607:f8b0:4864:20::1036]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1osF6d-002I2e-GR for linux-arm-kernel@lists.infradead.org; Tue, 08 Nov 2022 03:16:57 +0000 Received: by mail-pj1-x1036.google.com with SMTP id l22-20020a17090a3f1600b00212fbbcfb78so16674600pjc.3 for ; Mon, 07 Nov 2022 19:16:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-disposition:mime-version:message-id:subject:cc:to:from:date :from:to:cc:subject:date:message-id:reply-to; bh=NCHZRMv72CNijBXvJ4zsMsCF3iCoVBcytqRG84UrlOQ=; b=jHA7NR14yIWY0FrfzNLcfo0aGMJZM+nYXsUyaR/pqN+N3jQUqEUc3H1tTcXsHZnu8q xo3mWVgWBJtvfV9xtLHBDoxI+3gEOHv7eyErepFvpYAIggxWrOksR9vqRY3elvAqX5sp f8FPLqTwidtLT2dX6z6xmnYD11H4aFh1CS8K8g+Z1jv6Al4sN1yq3CLjtEqNUZUMITpL NKwXFRnCoahkCCehIK4HqHWS5poeRq91QJGDYQA67hP7Y6qK0645BGLik0vBpGd59XQ4 1ivg6oyRW8qDZuwnLnartRSCcEo2ME7Ffiaj+8YqlFo4Sx+DPlkra43VYc7apP7UBwaN 0RNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-disposition:mime-version:message-id:subject:cc:to:from:date :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=NCHZRMv72CNijBXvJ4zsMsCF3iCoVBcytqRG84UrlOQ=; b=nVEF6Cza4R6zeRE0SKhpDKkgntn93KOQ9zOKjzI/V3AOo4w//2HrAgXjsiTKlAqHWl QlUN6wkXjwCsn+OCKGHBE22feUwxcaN+utHLguqAC/WDuNyeiBH+ay1sFR1PugD6dobh 00lHG3aXYaoPodEPP6y05/RFLUHvGYXYIlwRdiiHQbdn+n0WMhlOGtzTqv4KfxqIZIKM LJMvPXph/45i+8s3SlAqekIMJm0uMNEWeDtebnEKmvrAZWgFLqZOfppNUPJmP7WmjR3f Eaq2pps7aN+o5+hx5vcAqK/9iDY1ZVNTMaCNoXN25Qqm4nAyKASdIV5cIrRPyPkDyI8R 0tSA== X-Gm-Message-State: ACrzQf1CNpC/ZMKh4qIOLN22HJAWi+b9G/YVTmKbUjlC2Ux9Xhm2Vh2j 5QX1adwyUAwHD030aGGi8fWeXnN41Hc= X-Google-Smtp-Source: AMsMyM4HZWrFNC5Yhnaiyipp2Q2b1huY1xTKqLQh9FET5IqRe4Q5oETkwZxvGqQAyIDdGHTisFvU5Q== X-Received: by 2002:a17:903:2289:b0:187:21f6:fdea with SMTP id b9-20020a170903228900b0018721f6fdeamr45261729plh.120.1667877413340; Mon, 07 Nov 2022 19:16:53 -0800 (PST) Received: from google.com ([2620:15c:9d:2:fb10:b5b0:232e:4afb]) by smtp.gmail.com with ESMTPSA id j7-20020a170902690700b00186e2b3e12fsm5632842plk.261.2022.11.07.19.16.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Nov 2022 19:16:52 -0800 (PST) Date: Mon, 7 Nov 2022 19:16:49 -0800 From: Dmitry Torokhov To: Qiang Zhao , Arnd Bergmann Cc: Li Yang , Greg Kroah-Hartman , Linus Walleij , Andy Shevchenko , linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org Subject: [PATCH] soc: fsl: qe: request pins non-exclusively Message-ID: MIME-Version: 1.0 Content-Disposition: inline X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221107_191655_593780_FB1C6909 X-CRM114-Status: GOOD ( 27.69 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Commit 84582f9ed090 ("soc: fsl: qe: Avoid using gpio_to_desc()") changed qe_pin_request() to request and hold GPIO corresponding to a given pin. Unfortunately this does not work, as fhci-hcd requests these GPIOs first, befor calling qe_pin_request() (see drivers/usb/host/fhci-hcd.c::of_fhci_probe()). To fix it change qe_pin_request() to request GPIOs non-exclusively, and free them once the code determines GPIO controller and offset for each GPIO/pin. Also reaching deep into gpiolib implementation is not the best idea. We should either export gpio_chip_hwgpio() or keep converting to the global gpio numbers space until we fix the driver to implement proper pin control. Fixes: 84582f9ed090 ("soc: fsl: qe: Avoid using gpio_to_desc()") Signed-off-by: Dmitry Torokhov Reviewed-by: Linus Walleij --- Compiled only, not tested on hardware. drivers/soc/fsl/qe/gpio.c | 71 ++++++++++++++++++------------------- drivers/usb/host/fhci-hcd.c | 2 +- include/soc/fsl/qe/qe.h | 5 +-- 3 files changed, 38 insertions(+), 40 deletions(-) diff --git a/drivers/soc/fsl/qe/gpio.c b/drivers/soc/fsl/qe/gpio.c index 0ee887f89deb..5bb71a2b5b7a 100644 --- a/drivers/soc/fsl/qe/gpio.c +++ b/drivers/soc/fsl/qe/gpio.c @@ -13,7 +13,7 @@ #include #include #include -#include +#include /* for of_mm_gpio_chip */ #include #include #include @@ -21,13 +21,6 @@ #include #include -/* - * FIXME: this is legacy code that is accessing gpiolib internals in order - * to implement a custom pin controller. The proper solution is to create - * a real combined pin control and GPIO driver in drivers/pinctrl. However - * this hack is here for legacy code reasons. - */ -#include "../../../gpio/gpiolib.h" struct qe_gpio_chip { struct of_mm_gpio_chip mm_gc; @@ -149,20 +142,19 @@ struct qe_pin { * something like qe_pio_controller. Someday. */ struct qe_gpio_chip *controller; - struct gpio_desc *gpiod; int num; }; /** * qe_pin_request - Request a QE pin - * @np: device node to get a pin from - * @index: index of a pin in the device tree + * @dev: device to get the pin from + * @index: index of the pin in the device tree * Context: non-atomic * * This function return qe_pin so that you could use it with the rest of * the QE Pin Multiplexing API. */ -struct qe_pin *qe_pin_request(struct device_node *np, int index) +struct qe_pin *qe_pin_request(struct device *dev, int index) { struct qe_pin *qe_pin; struct gpio_chip *gc; @@ -171,40 +163,46 @@ struct qe_pin *qe_pin_request(struct device_node *np, int index) qe_pin = kzalloc(sizeof(*qe_pin), GFP_KERNEL); if (!qe_pin) { - pr_debug("%s: can't allocate memory\n", __func__); + dev_dbg(dev, "%s: can't allocate memory\n", __func__); return ERR_PTR(-ENOMEM); } - gpiod = fwnode_gpiod_get_index(of_fwnode_handle(np), NULL, index, GPIOD_ASIS, "qe"); - if (IS_ERR(gpiod)) { - err = PTR_ERR(gpiod); - goto err0; - } - if (!gpiod) { - err = -EINVAL; + /* + * Request gpio as nonexclusive as it was likely was reserved by + * the caller, and we are not planning on controlling it, we only + * need the descriptor to the to the gpio chip structure. + */ + gpiod = gpiod_get_index(dev, NULL, index, + GPIOD_ASIS | GPIOD_FLAGS_BIT_NONEXCLUSIVE); + err = PTR_ERR_OR_ZERO(gpiod); + if (err) goto err0; - } + gc = gpiod_to_chip(gpiod); if (WARN_ON(!gc)) { err = -ENODEV; goto err0; - } - qe_pin->gpiod = gpiod; - qe_pin->controller = gpiochip_get_data(gc); - /* - * FIXME: this gets the local offset on the gpio_chip so that the driver - * can manipulate pin control settings through its custom API. The real - * solution is to create a real pin control driver for this. - */ - qe_pin->num = gpio_chip_hwgpio(gpiod); - - if (!fwnode_device_is_compatible(gc->fwnode, "fsl,mpc8323-qe-pario-bank")) { - pr_debug("%s: tried to get a non-qe pin\n", __func__); - gpiod_put(gpiod); + } else if (!fwnode_device_is_compatible(gc->fwnode, + "fsl,mpc8323-qe-pario-bank")) { + dev_dbg(dev, "%s: tried to get a non-qe pin\n", __func__); err = -EINVAL; - goto err0; + } else { + qe_pin->controller = gpiochip_get_data(gc); + /* + * FIXME: this gets the local offset on the gpio_chip so that + * the driver can manipulate pin control settings through its + * custom API. The real solution is to create a real pin control + * driver for this. + */ + qe_pin->num = desc_to_gpio(gpiod) - gc->base; } - return qe_pin; + + /* We no longer need this descriptor */ + gpiod_put(gpiod); + + if (!err) + return qe_pin; + err0: kfree(qe_pin); pr_debug("%s failed with status %d\n", __func__, err); @@ -222,7 +220,6 @@ EXPORT_SYMBOL(qe_pin_request); */ void qe_pin_free(struct qe_pin *qe_pin) { - gpiod_put(qe_pin->gpiod); kfree(qe_pin); } EXPORT_SYMBOL(qe_pin_free); diff --git a/drivers/usb/host/fhci-hcd.c b/drivers/usb/host/fhci-hcd.c index 95a44462bed0..1f666804fa91 100644 --- a/drivers/usb/host/fhci-hcd.c +++ b/drivers/usb/host/fhci-hcd.c @@ -651,7 +651,7 @@ static int of_fhci_probe(struct platform_device *ofdev) } for (j = 0; j < NUM_PINS; j++) { - fhci->pins[j] = qe_pin_request(node, j); + fhci->pins[j] = qe_pin_request(dev, j); if (IS_ERR(fhci->pins[j])) { ret = PTR_ERR(fhci->pins[j]); dev_err(dev, "can't get pin %d: %d\n", j, ret); diff --git a/include/soc/fsl/qe/qe.h b/include/soc/fsl/qe/qe.h index b02e9fe69146..eb5079904cc8 100644 --- a/include/soc/fsl/qe/qe.h +++ b/include/soc/fsl/qe/qe.h @@ -172,14 +172,15 @@ static inline int par_io_data_set(u8 port, u8 pin, u8 val) { return -ENOSYS; } /* * Pin multiplexing functions. */ +struct device; struct qe_pin; #ifdef CONFIG_QE_GPIO -extern struct qe_pin *qe_pin_request(struct device_node *np, int index); +extern struct qe_pin *qe_pin_request(struct device *dev, int index); extern void qe_pin_free(struct qe_pin *qe_pin); extern void qe_pin_set_gpio(struct qe_pin *qe_pin); extern void qe_pin_set_dedicated(struct qe_pin *pin); #else -static inline struct qe_pin *qe_pin_request(struct device_node *np, int index) +static inline struct qe_pin *qe_pin_request(struct device *dev, int index) { return ERR_PTR(-ENOSYS); }