From patchwork Sat Jun 29 17:51:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 13716981 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B4FADC30659 for ; Sat, 29 Jun 2024 17:52:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=OkOxO7czf0AzCfij/eBmMy0lU2OUt22cHe/e0cCc2nQ=; b=m6AD5cXf3v0oIXoEwKJTNpVTSf sLHt//Gtpu0tiwmWHfUmyGRs6Z4Ggg3cw9LrfV9wprFaOpRe69JEbb/O6SruppaorPWcFvlKVF3+a VfyopSr1tpoclkOk2vn5b0SIa+Yqip1VU7BzieX1mJ+eHMupx3G6ojccvIwU6SOswww+UjmkNIwQR IZZRTeg+GeL7UW9b5PBzTRzDH7M6+137JuzYBaX/zwXNe+B3gSH7ozayQH9Y8ZftQdqy8P24T799x uCntlzMf17Sl/d6GRuGSkGOrD15sbw3DuoM8n/nIx/3Ws3oxcjKZ7WJPHk2vR1nZ3CqXiaAR8lIbm 6ZymS0og==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sNcFZ-0000000Gk4y-2x0s; Sat, 29 Jun 2024 17:52:37 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sNcFO-0000000Gk2W-3F5s; Sat, 29 Jun 2024 17:52:28 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id 6F29A60B4E; Sat, 29 Jun 2024 17:52:17 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id C273AC2BBFC; Sat, 29 Jun 2024 17:52:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1719683537; bh=gVIxk8cHCVHUdA3fTQzmUY1+r/VjucLVQod4LejfzhI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TTs49XYfP3ql5lIR6MW6ictTaIjmRBmIZoBsUXFdretopDobLw2UkMRTJ0BFLJ+3o 9dBCeW6gnK5+gjDVs7V2t52KeL/3Yn6xIfrzt0oK7ACLQwZ/iX5xHSf+PkjQaNkmNu lHrFVM1icb731iQ1EdvvMDIWOQVdsrTPF82JEV/Wn561vvtpZTAJJ732mseq544Vr7 TU2Tmn0WEoKh7x2V11PPo4Mvw2i3yu+8YU2bVO7tuzWk81BPh6g36s6QdZHMJm+N7y GLpr9BLHSpmOWLdK8ac0iqpn8AaGqgiT5mgV4osMjftqSptjXM0GhOupfvGmNNtJYj tQ2lczTcCjtEA== From: Lorenzo Bianconi To: linux-phy@lists.infradead.org Cc: vkoul@kernel.org, kishon@kernel.org, lorenzo.bianconi83@gmail.com, conor@kernel.org, linux-arm-kernel@lists.infradead.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, devicetree@vger.kernel.org, nbd@nbd.name, john@phrozen.org, dd@embedd.com, catalin.marinas@arm.com, will@kernel.org, upstream@airoha.com, angelogioacchino.delregno@collabora.com Subject: [PATCH 1/2] dt-bindings: phy: airoha: Add dtime and Rx AEQ IO registers Date: Sat, 29 Jun 2024 19:51:48 +0200 Message-ID: X-Mailer: git-send-email 2.45.2 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240629_105226_867075_0D5BA04E X-CRM114-Status: UNSURE ( 7.41 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Introduce Tx-Rx detection time and Rx AEQ mappings in Airoha EN7581 PCIe-PHY binding. This change is not introducing any backward compatibility issue since the EN7581 dts is not upstream yet. Signed-off-by: Lorenzo Bianconi Acked-by: Conor Dooley --- .../bindings/phy/airoha,en7581-pcie-phy.yaml | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/airoha,en7581-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/airoha,en7581-pcie-phy.yaml index e26c30d17ff0..98fcb1b364de 100644 --- a/Documentation/devicetree/bindings/phy/airoha,en7581-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/airoha,en7581-pcie-phy.yaml @@ -21,12 +21,18 @@ properties: - description: PCIE analog base address - description: PCIE lane0 base address - description: PCIE lane1 base address + - description: PCIE lane0 detection time base address + - description: PCIE lane1 detection time base address + - description: PCIE Rx AEQ base address reg-names: items: - const: csr-2l - const: pma0 - const: pma1 + - const: p0-xr-dtime + - const: p1-xr-dtime + - const: rx-aeq "#phy-cells": const: 0 @@ -52,7 +58,12 @@ examples: #phy-cells = <0>; reg = <0x0 0x1fa5a000 0x0 0xfff>, <0x0 0x1fa5b000 0x0 0xfff>, - <0x0 0x1fa5c000 0x0 0xfff>; - reg-names = "csr-2l", "pma0", "pma1"; + <0x0 0x1fa5c000 0x0 0xfff>, + <0x0 0x1fc10044 0x0 0x4>, + <0x0 0x1fc30044 0x0 0x4>, + <0x0 0x1fc15030 0x0 0x104>; + reg-names = "csr-2l", "pma0", "pma1", + "p0-xr-dtime", "p1-xr-dtime", + "rx-aeq"; }; };