From patchwork Thu Jun 19 21:15:13 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chalamarla, Tirumalesh" X-Patchwork-Id: 4386181 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 8693A9F1D6 for ; Thu, 19 Jun 2014 21:19:38 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 999A8203AD for ; Thu, 19 Jun 2014 21:19:37 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id ABD2E203AB for ; Thu, 19 Jun 2014 21:19:36 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WxjhM-0001gR-Ft; Thu, 19 Jun 2014 21:16:44 +0000 Received: from mail-bl2lp0206.outbound.protection.outlook.com ([207.46.163.206] helo=na01-bl2-obe.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WxjhH-0001aa-Lr for linux-arm-kernel@lists.infradead.org; Thu, 19 Jun 2014 21:16:41 +0000 Received: from BY2PR07MB203.namprd07.prod.outlook.com (10.242.46.16) by BY2PR07MB203.namprd07.prod.outlook.com (10.242.46.16) with Microsoft SMTP Server (TLS) id 15.0.954.9; Thu, 19 Jun 2014 21:15:14 +0000 Received: from BY2PR07MB203.namprd07.prod.outlook.com ([169.254.13.8]) by BY2PR07MB203.namprd07.prod.outlook.com ([169.254.13.8]) with mapi id 15.00.0954.000; Thu, 19 Jun 2014 21:15:14 +0000 From: "Chalamarla, Tirumalesh" To: Andre Przywara , "linux-arm-kernel@lists.infradead.org" , "kvmarm@lists.cs.columbia.edu" , "kvm@vger.kernel.org" Subject: RE: [PATCH 04/14] arm/arm64: KVM: wrap 64 bit MMIO accesses with two 32 bit ones Thread-Topic: [PATCH 04/14] arm/arm64: KVM: wrap 64 bit MMIO accesses with two 32 bit ones Thread-Index: AQHPi6NiSZ1XVk9FMke+XLF5vvIfCpt4711w Date: Thu, 19 Jun 2014 21:15:13 +0000 Message-ID: References: <1403171152-24067-1-git-send-email-andre.przywara@arm.com> <1403171152-24067-5-git-send-email-andre.przywara@arm.com> In-Reply-To: <1403171152-24067-5-git-send-email-andre.przywara@arm.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [64.2.3.195] x-microsoft-antispam: BL:0; ACTION:Default; RISK:Low; SCL:0; SPMLVL:NotSpam; PCL:0; RULEID: x-forefront-prvs: 02475B2A01 x-forefront-antispam-report: SFV:NSPM; SFS:(6009001)(428001)(377454003)(13464003)(199002)(189002)(15975445006)(77982001)(101416001)(99396002)(87936001)(50986999)(4396001)(2171001)(83072002)(76576001)(74502001)(76482001)(85852003)(106116001)(80022001)(31966008)(74662001)(2656002)(33646001)(66066001)(76176999)(79102001)(19580395003)(83322001)(19580405001)(21056001)(81542001)(77096002)(74316001)(105586002)(81342001)(54356999)(46102001)(64706001)(20776003)(86362001)(95666004)(85306003)(99286002)(2201001)(92566001)(24736002); DIR:OUT; SFP:; SCL:1; SRVR:BY2PR07MB203; H:BY2PR07MB203.namprd07.prod.outlook.com; FPR:; MLV:sfv; PTR:InfoNoRecords; A:1; MX:1; LANG:en; received-spf: None (: caviumnetworks.com does not designate permitted sender hosts) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Tirumalesh.Chalamarla@caviumnetworks.com; MIME-Version: 1.0 X-OriginatorOrg: caviumnetworks.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140619_141639_914779_20D5B0FC X-CRM114-Status: GOOD ( 17.98 ) X-Spam-Score: -0.8 (/) Cc: "christoffer.dall@linaro.org" X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP -----Original Message----- From: kvmarm-bounces@lists.cs.columbia.edu [mailto:kvmarm-bounces@lists.cs.columbia.edu] On Behalf Of Andre Przywara Sent: Thursday, June 19, 2014 2:46 AM To: linux-arm-kernel@lists.infradead.org; kvmarm@lists.cs.columbia.edu; kvm@vger.kernel.org Cc: christoffer.dall@linaro.org Subject: [PATCH 04/14] arm/arm64: KVM: wrap 64 bit MMIO accesses with two 32 bit ones Some GICv3 registers can and will be accessed as 64 bit registers. Currently the register handling code can only deal with 32 bit accesses, so we do two consecutive calls to cover this. Signed-off-by: Andre Przywara --- virt/kvm/arm/vgic.c | 48 +++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 45 insertions(+), 3 deletions(-) * @run: pointer to the kvm_run structure @@ -936,10 +978,10 @@ static bool vgic_handle_mmio_range(struct kvm_vcpu *vcpu, struct kvm_run *run, spin_lock(&vcpu->kvm->arch.vgic.lock); offset -= range->base; if (vgic_validate_access(dist, range, offset)) { - updated_state = range->handle_mmio(vcpu, mmio, offset); + updated_state = call_range_handler(vcpu, mmio, offset, range); } else { - vgic_reg_access(mmio, NULL, offset, - ACCESS_READ_RAZ | ACCESS_WRITE_IGNORED); + if (!mmio->is_write) + memset(mmio->data, 0, mmio->len); What is the use of this memset. updated_state = false; } spin_unlock(&vcpu->kvm->arch.vgic.lock); -- 1.7.9.5 diff --git a/virt/kvm/arm/vgic.c b/virt/kvm/arm/vgic.c index 4c6b212..b3cf4c7 100644 --- a/virt/kvm/arm/vgic.c +++ b/virt/kvm/arm/vgic.c @@ -906,6 +906,48 @@ static bool vgic_validate_access(const struct vgic_dist *dist, } /* + * Call the respective handler function for the given range. + * We split up any 64 bit accesses into two consecutive 32 bit + * handler calls and merge the result afterwards. + */ +static bool call_range_handler(struct kvm_vcpu *vcpu, + struct kvm_exit_mmio *mmio, + unsigned long offset, + const struct mmio_range *range) { + u32 *data32 = (void *)mmio->data; + struct kvm_exit_mmio mmio32; + bool ret; + + if (likely(mmio->len <= 4)) + return range->handle_mmio(vcpu, mmio, offset); + + /* + * We assume that any access greater than 4 bytes is actually + * 8 bytes long, caused by a 64-bit access + */ + + mmio32.len = 4; + mmio32.is_write = mmio->is_write; + + mmio32.phys_addr = mmio->phys_addr + 4; + if (mmio->is_write) + *(u32 *)mmio32.data = data32[1]; + ret = range->handle_mmio(vcpu, &mmio32, offset + 4); + if (!mmio->is_write) + data32[1] = *(u32 *)mmio32.data; + + mmio32.phys_addr = mmio->phys_addr; + if (mmio->is_write) + *(u32 *)mmio32.data = data32[0]; + ret |= range->handle_mmio(vcpu, &mmio32, offset); + if (!mmio->is_write) + data32[0] = *(u32 *)mmio32.data; + + return ret; +} Any reason to use two 32 bits instead of one 64 bit. AArch32 on ARMv8 may be. + +/* * vgic_handle_mmio_range - handle an in-kernel MMIO access * @vcpu: pointer to the vcpu performing the access