From patchwork Thu Jan 4 09:40:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Wang X-Patchwork-Id: 10144387 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 107B16034B for ; Thu, 4 Jan 2018 09:57:55 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id ED0AD283B9 for ; Thu, 4 Jan 2018 09:57:54 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E1C3F2841C; Thu, 4 Jan 2018 09:57:54 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, RCVD_IN_DNSWL_MED, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 526A8283B9 for ; Thu, 4 Jan 2018 09:57:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=e/XKx1wagd/K3ggLGh1risFyvHckDHXDxftTBvJ1tIc=; b=IfZk+6r7dWP4Pw eNfcgALGrixs42pUB1Jp9RqHI2t7QKbTl1qqx3LgAYDWcfTIjaJnadfmyeGRdUvHyRhV89SHuW8ER SLQtWSZ8FnH7zazit7zFqw2ySSaFnC+0PsxsUs0bRi4KCGxTqR5stby9Chu9vPQdn/r3aiE8irUJN qeWKKzuGv68DwozcnSLzpc45sY4UD7JHr97IX5RG2izW9hjszbXEVVYrjI6Q93HxrUwOdcjwr+8MG YHypM+Z5ZGaomrMWprl5gf1Bi63eMy95WmaQfHEgpElEeXmrxWf6c/u9vh3XPTx8F89PaibqZNthY wsbzkkePShg1ZVfnCWow==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.89 #1 (Red Hat Linux)) id 1eX2HU-0006zj-3p; Thu, 04 Jan 2018 09:57:48 +0000 Received: from [210.61.82.183] (helo=mailgw01.mediatek.com) by bombadil.infradead.org with esmtps (Exim 4.89 #1 (Red Hat Linux)) id 1eX21e-0000OI-CF; Thu, 04 Jan 2018 09:41:35 +0000 X-UUID: 72a9e18dcd534be2819a8240b7c31c7f-20180104 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 668792039; Thu, 04 Jan 2018 17:41:11 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs08n1.mediatek.inc (172.21.101.55) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Thu, 4 Jan 2018 17:41:10 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Thu, 4 Jan 2018 17:41:10 +0800 From: To: , , , , Subject: [PATCH 08/12] arm64: dts: mt7622: add SoC and peripheral related device nodes Date: Thu, 4 Jan 2018 17:40:58 +0800 Message-ID: X-Mailer: git-send-email 1.7.9.5 In-Reply-To: References: MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180104_014126_904089_72FEF251 X-CRM114-Status: UNSURE ( 8.81 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew-CT Chen , Jun Gao , Leilk Liu , Zhiyong Tao , Sean Wang , linux-kernel@vger.kernel.org, Zhi Mao , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Sean Wang Add watchdog, rtc, auxadc, cir, efuse, rng, uart[1-4], pwm, i2c[0-2], spi[0-1] and btif nodes Signed-off-by: Sean Wang Cc: Andrew-CT Chen Cc: Zhiyong Tao Cc: Zhi Mao Cc: Jun Gao Cc: Leilk Liu Cc: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 54 ++++++++ arch/arm64/boot/dts/mediatek/mt7622.dtsi | 194 +++++++++++++++++++++++++++ 2 files changed, 248 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts index 4762168..3b2eacc 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts @@ -235,6 +235,34 @@ }; }; +&btif { + status = "okay"; +}; + +&cir { + pinctrl-names = "default"; + pinctrl-0 = <&irrx_pins>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + status = "okay"; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm7_pins>; + status = "okay"; +}; + &pwrap { pinctrl-names = "default"; pinctrl-0 = <&pmic_bus_pins>; @@ -242,6 +270,32 @@ status = "okay"; }; +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spic0_pins>; + status = "okay"; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spic1_pins>; + status = "okay"; +}; + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "okay"; +}; + +&watchdog { + pinctrl-names = "default"; + pinctrl-0 = <&watchdog_pins>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi index 3b6f082..681c87a 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi @@ -173,6 +173,16 @@ clock-names = "hif_sel"; }; + cir: cir@10009000 { + compatible = "mediatek,mt7622-cir"; + reg = <0 0x10009000 0 0x1000>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_IRRX_PD>, + <&topckgen CLK_TOP_AXI_SEL>; + clock-names = "clk", "bus"; + status = "disabled"; + }; + sysirq: interrupt-controller@10200620 { compatible = "mediatek,mt7622-sysirq", "mediatek,mt6577-sysirq"; @@ -182,6 +192,18 @@ reg = <0 0x10200620 0 0x20>; }; + efuse: efuse@10206000 { + compatible = "mediatek,mt7622-efuse", + "mediatek,efuse"; + reg = <0 0x10206000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + thermal_calibration: calib@198 { + reg = <0x198 0x8>; + }; + }; + apmixedsys: apmixedsys@10209000 { compatible = "mediatek,mt7622-apmixedsys", "syscon"; @@ -196,6 +218,14 @@ #clock-cells = <1>; }; + rng: rng@1020f000 { + compatible = "mediatek,mt7622-rng", + "mediatek,mt7623-rng"; + reg = <0 0x1020f000 0 0x1000>; + clocks = <&infracfg CLK_INFRA_TRNG>; + clock-names = "rng"; + }; + pio: pinctrl@10211000 { compatible = "mediatek,mt7622-pinctrl"; reg = <0 0x10211000 0 0x1000>; @@ -203,6 +233,21 @@ #gpio-cells = <2>; }; + watchdog: watchdog@10212000 { + compatible = "mediatek,mt7622-wdt", + "mediatek,mt6589-wdt"; + reg = <0 0x10212000 0 0x800>; + }; + + rtc: rtc@10212800 { + compatible = "mediatek,mt7622-rtc", + "mediatek,soc-rtc"; + reg = <0 0x10212800 0 0x200>; + interrupts = ; + clocks = <&topckgen CLK_TOP_RTC>; + clock-names = "rtc"; + }; + gic: interrupt-controller@10300000 { compatible = "arm,gic-400"; interrupt-controller; @@ -214,6 +259,14 @@ <0 0x10360000 0 0x2000>; }; + auxadc: adc@11001000 { + compatible = "mediatek,mt7622-auxadc"; + reg = <0 0x11001000 0 0x1000>; + clocks = <&pericfg CLK_PERI_AUXADC_PD>; + clock-names = "main"; + #io-channel-cells = <1>; + }; + uart0: serial@11002000 { compatible = "mediatek,mt7622-uart", "mediatek,mt6577-uart"; @@ -225,6 +278,147 @@ status = "disabled"; }; + uart1: serial@11003000 { + compatible = "mediatek,mt7622-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11003000 0 0x400>; + interrupts = ; + clocks = <&topckgen CLK_TOP_UART_SEL>, + <&pericfg CLK_PERI_UART1_PD>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart2: serial@11004000 { + compatible = "mediatek,mt7622-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11004000 0 0x400>; + interrupts = ; + clocks = <&topckgen CLK_TOP_UART_SEL>, + <&pericfg CLK_PERI_UART2_PD>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart3: serial@11005000 { + compatible = "mediatek,mt7622-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11005000 0 0x400>; + interrupts = ; + clocks = <&topckgen CLK_TOP_UART_SEL>, + <&pericfg CLK_PERI_UART3_PD>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + pwm: pwm@11006000 { + compatible = "mediatek,mt7622-pwm"; + reg = <0 0x11006000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_PWM_SEL>, + <&pericfg CLK_PERI_PWM_PD>, + <&pericfg CLK_PERI_PWM1_PD>, + <&pericfg CLK_PERI_PWM2_PD>, + <&pericfg CLK_PERI_PWM3_PD>, + <&pericfg CLK_PERI_PWM4_PD>, + <&pericfg CLK_PERI_PWM5_PD>, + <&pericfg CLK_PERI_PWM6_PD>; + clock-names = "top", "main", "pwm1", "pwm2", "pwm3", "pwm4", + "pwm5", "pwm6"; + status = "disabled"; + }; + + i2c0: i2c@11007000 { + compatible = "mediatek,mt7622-i2c"; + reg = <0 0x11007000 0 0x90>, + <0 0x11000100 0 0x80>; + interrupts = ; + clock-div = <16>; + clocks = <&pericfg CLK_PERI_I2C0_PD>, + <&pericfg CLK_PERI_AP_DMA_PD>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@11008000 { + compatible = "mediatek,mt7622-i2c"; + reg = <0 0x11008000 0 0x90>, + <0 0x11000180 0 0x80>; + interrupts = ; + clock-div = <16>; + clocks = <&pericfg CLK_PERI_I2C1_PD>, + <&pericfg CLK_PERI_AP_DMA_PD>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@11009000 { + compatible = "mediatek,mt7622-i2c"; + reg = <0 0x11009000 0 0x90>, + <0 0x11000200 0 0x80>; + interrupts = ; + clock-div = <16>; + clocks = <&pericfg CLK_PERI_I2C2_PD>, + <&pericfg CLK_PERI_AP_DMA_PD>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi0: spi@1100a000 { + compatible = "mediatek,mt7622-spi"; + reg = <0 0x1100a000 0 0x100>; + interrupts = ; + clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, + <&topckgen CLK_TOP_SPI0_SEL>, + <&pericfg CLK_PERI_SPI0_PD>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + btif: serial@1100c000 { + compatible = "mediatek,mt7622-btif", + "mediatek,mtk-btif"; + reg = <0 0x1100c000 0 0x1000>; + interrupts = ; + clocks = <&pericfg CLK_PERI_BTIF_PD>; + clock-names = "main"; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + spi1: spi@11016000 { + compatible = "mediatek,mt7622-spi"; + reg = <0 0x11016000 0 0x100>; + interrupts = ; + clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, + <&topckgen CLK_TOP_SPI1_SEL>, + <&pericfg CLK_PERI_SPI1_PD>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart4: serial@11019000 { + compatible = "mediatek,mt7622-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11019000 0 0x400>; + interrupts = ; + clocks = <&topckgen CLK_TOP_UART_SEL>, + <&pericfg CLK_PERI_UART4_PD>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + ssusbsys: ssusbsys@1a000000 { compatible = "mediatek,mt7622-ssusbsys", "syscon";