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Tue, 28 May 2024 01:10:00 -0700 From: Nicolin Chen To: , , CC: , , , , , , , Subject: [PATCH v8 3/6] iommu/arm-smmu-v3: Enforce arm_smmu_cmdq_build_sync_cmd Date: Tue, 28 May 2024 01:09:51 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF00000016:EE_|CH3PR12MB7642:EE_ X-MS-Office365-Filtering-Correlation-Id: 1ffbd68e-a013-493c-fdf8-08dc7eed985c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|36860700004|82310400017|1800799015|376005; X-Microsoft-Antispam-Message-Info: e01tgyz0fSHVSoPc8dlMFt+D50IZxWQPGcHuXTDujouf2mCOYyGAyR0nPOQ0kTEXacIWZLXD5ZajS15T/4el2ty8He9x4M1I4xhDAdtM08g/lcrC9xcCP4Vbqiw1y4AdWya6jhayDRpRlPN/qgvp/eQG3yITdTaoMC1/Lt7Uz4WcbHdGqJWOXN0GjocIGh2R7Z1M5cgOQ7C+M4bV+g5K/LAqxe8e5QHlf+u7TAlxloOr8K+wWAYYLhCukFMr3dVd0O9gQB6af6rhFVzZt0TaYsNq5EujQxY/KqrVTQGuqv5Q+7pbuqPuxmWJytGzK4GTItOGUM/xwfcCSMX/F+aGtRaon2bjoVFcIqJas498dH9ASRC9INdfilKJRF0Q+r80wKV6JCfMSLgc8YZl7FZ+Eg4XPckfcdd8JRfgU81JPW7cTGLJLLKKlXuCtqjltUD0tZjnMQBbrAlFMW0gnw/oweFFPQBUTQVSsbV6yH0lU1YhwNRTAB1piQMsC6lV0EKZU0T9Y0B59fBxuPxmv2CngB1qEltx8MMr6YkbLKF6clYhQNjSCYF1D8j5ZmwoU3j8O8uks76zkukZtIbS+2nNQE0EAtK5lXfzscU0xzPgaqvtXDnrhmQ9brJU6u5n0Itu9WJ6HtmVk8aR890g6egCh0N/A1rGVQP9pwTaVbtNESDMVp5HTUanj2XlK3S3YL94S5R4KRj3ODr6481SOOZuIy0mTXcXyiRjBMWXIttet1aI/orZfW1OXNQRgmBuzqYskM0nF2bV4AaFh9HvxgU+yUa0uPpSYziMvE3jnjb/wh11jaazRkZmdQjL86hBVaLiYLLNLqHxNhsXJL8aoSeG2fE+O33Sq6NTm/O5pVkKsox74kuyTl8h7xkwjhQGKEurvr0Htlo0X1kqMsRWbmJ493LJORA+FLwx/FsMJhlbEt2Kp4StMNXLlHXGET1lmj1nXd+6sGhzaw2TgzGFobRcURAOC67Nz69dsvx4fXS8Adjjn8eO/zdC9VsffEKu8Hs4cae3ms82pikdbvmXiA7pK4NjQh+IrX7YbmG4LeHW4VrA5Z/vlNjFWRP0mSFDQTyXRql7VVib1CpNrsjB4RaiIMmXe4sPKV8XmgOUNyvv/g/X6n6t3TJrjvy2VnCD+J8KNTpin6Xts4UYE4ku+NUmJ/2mzsppexAvGOa5K0+WrCStZRBYKI2LhP7wSajaDobZoQ0LSaXYm+CTwKw+IXEPHbkx1lWTsPi4X9PJeKIjnDFYzGZT6V+NwvNPO41g96s5sIJ5uGw0boWHtO8HeNVYMx+tsH7KRgZOC5MO1XK7GxR/GBxOgOWQkZ0aNMWR7X9X2/TRrq+w45fJ1Z6HxJB1C44/GBcPDeszdPsGRtPLKkO3NLrxkG3I3WzlKP+Q1CoQ X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230031)(36860700004)(82310400017)(1800799015)(376005);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 May 2024 08:10:10.6785 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1ffbd68e-a013-493c-fdf8-08dc7eed985c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF00000016.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB7642 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240528_011023_303544_A1456A20 X-CRM114-Status: GOOD ( 18.07 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org There is an existing arm_smmu_cmdq_build_sync_cmd() so the driver should call it at all places other than going through arm_smmu_cmdq_build_cmd() separately. This helps the following patch that adds a CS_NONE quirk for tegra241-cmdqv driver. Note that this changes the type of CMD_SYNC in __arm_smmu_cmdq_skip_err, in ARM_SMMU_OPT_MSIPOLL=true case, from previously a non-MSI one to now an MSI one that is proven to still work using a hacking test: nvme: Adding to iommu group 10 nvme: --------hacking----------- arm-smmu-v3: unexpected global error reported (0x00000001), this could be serious arm-smmu-v3: CMDQ error (cons 0x01000022): Illegal command arm-smmu-v3: skipping command in error state: arm-smmu-v3: 0x0000000000000000 arm-smmu-v3: 0x0000000000000000 nvme: -------recovered---------- nvme nvme0: 72/0/0 default/read/poll queues nvme0n1: p1 p2 Suggested-by: Jason Gunthorpe Reviewed-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 36 ++++++++------------- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 3 -- 2 files changed, 13 insertions(+), 26 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index dc8e9a48fe62..c864c634cd23 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -325,16 +325,6 @@ static int arm_smmu_cmdq_build_cmd(u64 *cmd, struct arm_smmu_cmdq_ent *ent) cmd[0] |= FIELD_PREP(CMDQ_RESUME_0_RESP, ent->resume.resp); cmd[1] |= FIELD_PREP(CMDQ_RESUME_1_STAG, ent->resume.stag); break; - case CMDQ_OP_CMD_SYNC: - if (ent->sync.msiaddr) { - cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_IRQ); - cmd[1] |= ent->sync.msiaddr & CMDQ_SYNC_1_MSIADDR_MASK; - } else { - cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_SEV); - } - cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_MSH, ARM_SMMU_SH_ISH); - cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_MSIATTR, ARM_SMMU_MEMATTR_OIWB); - break; default: return -ENOENT; } @@ -350,20 +340,23 @@ static struct arm_smmu_cmdq *arm_smmu_get_cmdq(struct arm_smmu_device *smmu) static void arm_smmu_cmdq_build_sync_cmd(u64 *cmd, struct arm_smmu_device *smmu, struct arm_smmu_queue *q, u32 prod) { - struct arm_smmu_cmdq_ent ent = { - .opcode = CMDQ_OP_CMD_SYNC, - }; + cmd[1] = 0; + cmd[0] = FIELD_PREP(CMDQ_0_OP, CMDQ_OP_CMD_SYNC) | + FIELD_PREP(CMDQ_SYNC_0_MSH, ARM_SMMU_SH_ISH) | + FIELD_PREP(CMDQ_SYNC_0_MSIATTR, ARM_SMMU_MEMATTR_OIWB); + + if (!(smmu->options & ARM_SMMU_OPT_MSIPOLL)) { + cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_SEV); + return; + } /* * Beware that Hi16xx adds an extra 32 bits of goodness to its MSI * payload, so the write will zero the entire command on that platform. */ - if (smmu->options & ARM_SMMU_OPT_MSIPOLL) { - ent.sync.msiaddr = q->base_dma + Q_IDX(&q->llq, prod) * - q->ent_dwords * 8; - } - - arm_smmu_cmdq_build_cmd(cmd, &ent); + cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_IRQ); + cmd[1] |= (q->base_dma + Q_IDX(&q->llq, prod) * q->ent_dwords * 8) & + CMDQ_SYNC_1_MSIADDR_MASK; } void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu, @@ -380,9 +373,6 @@ void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu, u64 cmd[CMDQ_ENT_DWORDS]; u32 cons = readl_relaxed(q->cons_reg); u32 idx = FIELD_GET(CMDQ_CONS_ERR, cons); - struct arm_smmu_cmdq_ent cmd_sync = { - .opcode = CMDQ_OP_CMD_SYNC, - }; dev_err(smmu->dev, "CMDQ error (cons 0x%08x): %s\n", cons, idx < ARRAY_SIZE(cerror_str) ? cerror_str[idx] : "Unknown"); @@ -416,7 +406,7 @@ void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu, dev_err(smmu->dev, "\t0x%016llx\n", (unsigned long long)cmd[i]); /* Convert the erroneous command into a CMD_SYNC */ - arm_smmu_cmdq_build_cmd(cmd, &cmd_sync); + arm_smmu_cmdq_build_sync_cmd(cmd, smmu, q, cons); queue_write(Q_ENT(q, cons), cmd, q->ent_dwords); } diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 8e4fbf4f50f3..180c0b1e0658 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -512,9 +512,6 @@ struct arm_smmu_cmdq_ent { } resume; #define CMDQ_OP_CMD_SYNC 0x46 - struct { - u64 msiaddr; - } sync; }; };