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Fri, 10 Jan 2025 19:32:54 -0800 From: Nicolin Chen To: , , , , , , CC: , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH RFCv2 04/13] irqchip: Have CONFIG_IRQ_MSI_IOMMU be selected by the irqchips that need it Date: Fri, 10 Jan 2025 19:32:20 -0800 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF0000C37E:EE_|BL3PR12MB9051:EE_ X-MS-Office365-Filtering-Correlation-Id: acd96c8b-7246-4f73-1a4e-08dd31f0a493 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|7416014|376014|82310400026; X-Microsoft-Antispam-Message-Info: vKA8YrTmgMJgbg2N9uPhirJCVK2Lj00HnaQWrdP9kDX2YScZ5b6I1bBUYrxPixsEt0ryAFVqvHkjbDv7nmj0+guR/1Z7b3DVLZhakmY6E13C/4Gtvv277A6kg9dwHGAypNcd4XjH3kERBx42L3w1rBuych87n54PloTfc1EqSMkDX+W/CFhoq7WCJbxNiBrA0UFgcguunnrm+qdyLRGVjxN5otHtH8r7m+u6hdAUogs/4VUIOh8fBmbUlUxXLGt1uzsPTTzVaTGuv0VEt01JeAn9XLGH90LDCZQp/ql93EvN991qZOpl+Rx9JgW34Nc+bGLp/iH+0IHB+SlRi2mZn0jngX9aapZ8J63tmAiad5lR4bbPx9jR7KtcHdfZziJpXbU3AObIJzp/k+oJlRyfktzLR8di6wmastn/We8aFm89yPR4xgWXqpuP2LW6PaK3Wf5QoyWCSTl1RSClWRcMXn4+RuYCl8eByLEUdtlChkMmAeCkDsl1zn3udrDC4HJbUCIT3RRi/HX3oxP+V4JR5tTswUwcQRHuDcw2NL+0ZQvwfsAF0AIzqBWhA5iNNNb8BieuzzWKqqyR829Ouycn5O9VeD0IXdLhy1Db2Atr9hG/AR7eWtWBUmo20AxWcx6HGhA/ulWHN8AFBEhGfKKC862sTM4ym8RdQLzXWPxs/D4+8FmxyrAQJ5NyfonXBWOo7Y+LoKR69Y7YfeCsnBXmq4zbvifA7vln9kcIJ0ljMZPGFtflnce00ZaS+i0IafGwzrp6b5oWXJ24TB8vcqu9B3LXsACgotVeCvy3r92Co7kQ3ZS0tpR4b3ZZJJyZues2TrbDMHcr/1CsD87/P9Y7xJseFzreoB09MwPulf3zkDEPUsIoNdsd+6OslIvgLe5y0MmVU0yKldRshfySubgzoiTkVfqkwGuDadRWN6tvbWWPpNtXr5ye/iaVzlZRG72ppWmFhWHUTCOZZFwY51zwigrqsJl1mmClvbImxMArUJQE00xBSqoUePBMzeO89lzqhraIhDM5gZwkUcpXv2ossE47orbP6jlWnEjubkzsg2YFYp6tSZWJOK7bTZMCWAcskxivMqSqgPh3tuKlUCgmWnh0Cyjqlbp4xCLGKbkR7fe/dCu0Ei386HyFO1hwT44ovm6DE2Np0VAt5DP1kn4m3w5JN9eR7/DaDr4LaRr9PRbkVXqHS9UYW/1XmHyyQA4tXfD19YcrvwTxvA+vdYOA7P55d9eTmYr5zrG/hNo8tLWiW9hHFPMvPpgPHOqYxfTFS2xgeZo4gBt/U0LP7ocl0oY125LH3EUpHyqIwuPwwWIuO9OIRhP8lz8OrePOf/jqOTkwifxXhB4tn36fsK4SE9ZYB3ATDUonuULqhexTs6xrwCWEfnpTgKl0aYJWRugzoL3G24vVFlr07KOE7uWFvnQ8+AnjMzzfP+8EXGTjP7/USfXQXEZLm7GlasOglyFPnkZb16CHX8+SQ8YroK1XVA== X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(7416014)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Jan 2025 03:32:57.8400 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: acd96c8b-7246-4f73-1a4e-08dd31f0a493 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF0000C37E.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR12MB9051 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250110_193303_347947_4F652DD6 X-CRM114-Status: GOOD ( 13.05 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Jason Gunthorpe Currently IRQ_MSI_IOMMU is selected if DMA_IOMMU is available to provide an implementation for iommu_dma_prepare/compose_msi_msg(). However it makes more sense for the irqchips that call prepare/compose to select it and that will trigger all the additional code and data to be compiled into the kernel. If IRQ_MSI_IOMMU is selected with no IOMMU side implementation then prepare/compose will be NOP stubs. If IRQ_MSI_IOMMU is not selected by an irqchip then the related code on the iommu side is compiled out. Signed-off-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/Kconfig | 1 - drivers/irqchip/Kconfig | 4 ++++ kernel/irq/Kconfig | 1 + 3 files changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig index 47c46e4b739e..b9a4f0521d71 100644 --- a/drivers/iommu/Kconfig +++ b/drivers/iommu/Kconfig @@ -154,7 +154,6 @@ config IOMMU_DMA select DMA_OPS_HELPERS select IOMMU_API select IOMMU_IOVA - select IRQ_MSI_IOMMU select NEED_SG_DMA_LENGTH select NEED_SG_DMA_FLAGS if SWIOTLB diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 9bee02db1643..758cbbf907aa 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -28,6 +28,7 @@ config ARM_GIC_V2M select ARM_GIC select IRQ_MSI_LIB select PCI_MSI + select IRQ_MSI_IOMMU config GIC_NON_BANKED bool @@ -38,12 +39,14 @@ config ARM_GIC_V3 select PARTITION_PERCPU select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP select HAVE_ARM_SMCCC_DISCOVERY + select IRQ_MSI_IOMMU config ARM_GIC_V3_ITS bool select GENERIC_MSI_IRQ select IRQ_MSI_LIB default ARM_GIC_V3 + select IRQ_MSI_IOMMU config ARM_GIC_V3_ITS_FSL_MC bool @@ -407,6 +410,7 @@ config LS_EXTIRQ config LS_SCFG_MSI def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE + select IRQ_MSI_IOMMU depends on PCI_MSI config PARTITION_PERCPU diff --git a/kernel/irq/Kconfig b/kernel/irq/Kconfig index 529adb1f5859..045b37073d4a 100644 --- a/kernel/irq/Kconfig +++ b/kernel/irq/Kconfig @@ -96,6 +96,7 @@ config GENERIC_MSI_IRQ bool select IRQ_DOMAIN_HIERARCHY +# irqchip drivers should select this if they call iommu_dma_prepare_msi() config IRQ_MSI_IOMMU bool