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Thu, 29 Aug 2024 15:34:47 -0700 From: Nicolin Chen To: CC: , , , , , , , , , Subject: [PATCH v14 05/10] iommu/arm-smmu-v3: Add ARM_SMMU_OPT_TEGRA241_CMDQV Date: Thu, 29 Aug 2024 15:34:34 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000397B4:EE_|IA1PR12MB7736:EE_ X-MS-Office365-Filtering-Correlation-Id: a65eec80-4590-41b6-e10a-08dcc87ad48a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: eHWmqBRSKKegDiSk43GTVHvonHghBZdpbhwc9rL0O1Ke2IF0p3iEi2VtKIDfd+qXVDrhHbY8ZXf9Fl7hrm85g+uqIzrG+rNgFbvl3L6C/VKTtpn9gasuqGN7Mj+KYM3V59PjiA6lrM7ufrtF3dyW3EAXfoybJv7sNmUE3m/0v5yn9AcdFi9DNtZuytHb1+RAZGgvsB6m2M20B1zFgYCZT6KLLYYDth2divoYOltDQ9AtBKHg6RLyXknTi3GW//igGq0nEo1KwT8b3lhFSZy7qQAMuUpbr4B8cGBmSxtoOx4OytoJV/feTjcse96XRY+MLGHXTwU2hLEgs+OvW9BFEyVgyOiFr867DQNOb/S4lyHkjrXWaMiLfo5+I+TE2L4vNuc3W3zVy+dDsYy4kjdq2/rs+TtD0I04L1s1Zl/uLHlRdIYfmzxiWXaFHReUA+x6pbMee3xRH+1DsGXJXwpCtbQ3gcLwNgl68LuB6kN+BGTlNLxiXUnAPm0YyqdeOQPFh8m3uXmQ58DgEqQv+J/69vgP/2XC9ljVQ4nanAYON3l7JCQaUtOXIKVXI4MMRB1xxpE240j0K+cu5ZvcKune/jCXVNgofnC3OJxtFp2CNalmhcNKxMPSNsMMg9FbwgP4gGJixqkZNkM/0ocZI+0BHLY/j1mcq3eQnt7ZgbdmuIUObzMDtVFsiiaJbr0QShmHjEB6Pmm269ab3Dgs25D+T0MYEmdBVygX0BZ/p01O1S4wo8Bea+bliS25kT2Z5yz0+3DQlyJqwF+jnNBb3RE4QD2AcKnnm7hBBMOQjzjQcJ+Ic61IsLkb9QlKstrEY7XumbNqrBqyIVim5zYhAocbvGXw8W/kEcPwzzarjY+300XgRkEP0CFA2PZ9eFdsfdE2PJwHdAKUS08dIbMIFBxl1ZJV8MTH232zCv5dX0LPgjgA3fF/ZBF/Nn+cP+uHr+rAhGr23oJm1ObpD4ZMm7kWgQtc+up5kWhRVdv71+sjVCPJ09yUH0SK4RM2D2E3Iuw08l8AInwbUuqx/CPKk4/txWrhq9M2OeBb0k20VIE7eut886TZ/d1x9YqGo5lhYrVBdhBJjYgiQcgV3gPN0RvHG6kpqX95U8nzEzqyIBw5qnVsgqloqQjGrMmJLs87+YS442c5GR7P/aNbgGLRuc553fk+JfJTiQWKyoYbNWIYUczwlZBLBRvqXVCtH5drT+1MXn8kzPjlvfeCZ9BekncNEnQn71r21wVYuFQW/ibgP5BGiDlMmljxwFzy/MHEp/NaW4YMGjsRGKV3iODh4z2hD5NVP+1V+c6LIz0ZdX6M3z3qknVXsT4uSOOD6wIaFM3j2E2cats+ZCeLtxEX092xHRlzN3c4i3poVfPb/2pkmBV4YdciGYpFHLDjDV3zA3B3hLyUHcvDxrej9CzyJZxm+MSZ2kqCVtNmhzGE4rIJsqgTR8hm5O7ruB5lzvR2vFhD X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(82310400026)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Aug 2024 22:35:05.5641 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a65eec80-4590-41b6-e10a-08dcc87ad48a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397B4.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB7736 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240829_153514_025950_5EB89E3F X-CRM114-Status: GOOD ( 14.06 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The CMDQV extension in NVIDIA Tegra241 SoC only supports CS_NONE in the CS field of CMD_SYNC. Add a new SMMU option to accommodate that. Suggested-by: Will Deacon Reviewed-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 16 +++++++++++++++- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 1 + 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 061a61f4ff0a..816f5937345a 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -351,6 +351,15 @@ static struct arm_smmu_cmdq *arm_smmu_get_cmdq(struct arm_smmu_device *smmu) return &smmu->cmdq; } +static bool arm_smmu_cmdq_needs_busy_polling(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq *cmdq) +{ + if (cmdq == &smmu->cmdq) + return false; + + return smmu->options & ARM_SMMU_OPT_TEGRA241_CMDQV; +} + static void arm_smmu_cmdq_build_sync_cmd(u64 *cmd, struct arm_smmu_device *smmu, struct arm_smmu_cmdq *cmdq, u32 prod) { @@ -369,6 +378,8 @@ static void arm_smmu_cmdq_build_sync_cmd(u64 *cmd, struct arm_smmu_device *smmu, } arm_smmu_cmdq_build_cmd(cmd, &ent); + if (arm_smmu_cmdq_needs_busy_polling(smmu, cmdq)) + u64p_replace_bits(cmd, CMDQ_SYNC_0_CS_NONE, CMDQ_SYNC_0_CS); } void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu, @@ -423,6 +434,8 @@ void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu, /* Convert the erroneous command into a CMD_SYNC */ arm_smmu_cmdq_build_cmd(cmd, &cmd_sync); + if (arm_smmu_cmdq_needs_busy_polling(smmu, cmdq)) + u64p_replace_bits(cmd, CMDQ_SYNC_0_CS_NONE, CMDQ_SYNC_0_CS); queue_write(Q_ENT(q, cons), cmd, q->ent_dwords); } @@ -706,7 +719,8 @@ static int arm_smmu_cmdq_poll_until_sync(struct arm_smmu_device *smmu, struct arm_smmu_cmdq *cmdq, struct arm_smmu_ll_queue *llq) { - if (smmu->options & ARM_SMMU_OPT_MSIPOLL) + if (smmu->options & ARM_SMMU_OPT_MSIPOLL && + !arm_smmu_cmdq_needs_busy_polling(smmu, cmdq)) return __arm_smmu_cmdq_poll_until_msi(smmu, cmdq, llq); return __arm_smmu_cmdq_poll_until_consumed(smmu, cmdq, llq); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 50efc804f91c..21f034f0ff4c 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -665,6 +665,7 @@ struct arm_smmu_device { #define ARM_SMMU_OPT_PAGE0_REGS_ONLY (1 << 1) #define ARM_SMMU_OPT_MSIPOLL (1 << 2) #define ARM_SMMU_OPT_CMDQ_FORCE_SYNC (1 << 3) +#define ARM_SMMU_OPT_TEGRA241_CMDQV (1 << 4) u32 options; struct arm_smmu_cmdq cmdq;