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+Device tree bindings for Zynq's OCM controller
+
+The OCM is divided to 4 64kB segments which can be separately configured
+to low or high location. Location is controlled via SLCR.
+
+Required properties:
+ compatible: Compatibility string. Must be "xlnx,zynq-ocmc-1.0".
+ reg: Specify the base and size of the OCMC registers in the memory map.
+ E.g.: reg = <0xf800c000 0x1000>;
+
+Example:
+ocmc: memory-controller@f800c000 {
+ compatible = "xlnx,zynq-ocmc-1.0";
+ interrupt-parent = <&intc>;
+ interrupts = <0 3 4>;
+ reg = <0xf800c000 0x1000>;
+};
Add binding for Zynq On Chip Memory controller driver which is taking care about On Chip Memory. Signed-off-by: Michal Simek <michal.simek@xilinx.com> --- Changes in v5: - Separate binding from the driver Changes in v4: None Changes in v3: None Changes in v2: None .../devicetree/bindings/arm/zynq/xlnx,zynq-ocmc.txt | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/zynq/xlnx,zynq-ocmc.txt -- 1.8.2.3