diff mbox series

arm64: dts: rockchip: Add RK3328 idle state

Message ID a8c83e705d387446ea8121516d410e38b2d9c57b.1577640736.git.robin.murphy@arm.com (mailing list archive)
State Mainlined
Commit 4f279f9fbca54464173240f7e73b145a136dfa1e
Headers show
Series arm64: dts: rockchip: Add RK3328 idle state | expand

Commit Message

Robin Murphy Dec. 29, 2019, 8:16 p.m. UTC 
Downstream RK3328 DTBs describe a CPU idle state matching that present
on other SoCs like RK3399. This works with upstream Trusted Firmware-A
too, so let's add it here.

Signed-off-by: Robin Murphy <robin.murphy@arm.com>
---
 arch/arm64/boot/dts/rockchip/rk3328.dtsi | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

Comments

Heiko Stuebner Dec. 31, 2019, 11:49 a.m. UTC | #1 
Am Sonntag, 29. Dezember 2019, 21:16:17 CET schrieb Robin Murphy:
> Downstream RK3328 DTBs describe a CPU idle state matching that present
> on other SoCs like RK3399. This works with upstream Trusted Firmware-A
> too, so let's add it here.
> 
> Signed-off-by: Robin Murphy <robin.murphy@arm.com>

applied for 5.6

Thanks
Heiko
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index 7df7daa188df..d71187cdd430 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -41,6 +41,7 @@ 
 			reg = <0x0 0x0>;
 			clocks = <&cru ARMCLK>;
 			#cooling-cells = <2>;
+			cpu-idle-states = <&CPU_SLEEP>;
 			dynamic-power-coefficient = <120>;
 			enable-method = "psci";
 			next-level-cache = <&l2>;
@@ -53,6 +54,7 @@ 
 			reg = <0x0 0x1>;
 			clocks = <&cru ARMCLK>;
 			#cooling-cells = <2>;
+			cpu-idle-states = <&CPU_SLEEP>;
 			dynamic-power-coefficient = <120>;
 			enable-method = "psci";
 			next-level-cache = <&l2>;
@@ -65,6 +67,7 @@ 
 			reg = <0x0 0x2>;
 			clocks = <&cru ARMCLK>;
 			#cooling-cells = <2>;
+			cpu-idle-states = <&CPU_SLEEP>;
 			dynamic-power-coefficient = <120>;
 			enable-method = "psci";
 			next-level-cache = <&l2>;
@@ -77,12 +80,26 @@ 
 			reg = <0x0 0x3>;
 			clocks = <&cru ARMCLK>;
 			#cooling-cells = <2>;
+			cpu-idle-states = <&CPU_SLEEP>;
 			dynamic-power-coefficient = <120>;
 			enable-method = "psci";
 			next-level-cache = <&l2>;
 			operating-points-v2 = <&cpu0_opp_table>;
 		};
 
+		idle-states {
+			entry-method = "psci";
+
+			CPU_SLEEP: cpu-sleep {
+				compatible = "arm,idle-state";
+				local-timer-stop;
+				arm,psci-suspend-param = <0x0010000>;
+				entry-latency-us = <120>;
+				exit-latency-us = <250>;
+				min-residency-us = <900>;
+			};
+		};
+
 		l2: l2-cache0 {
 			compatible = "cache";
 		};