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Thu, 9 Mar 2023 02:54:44 -0800 From: Nicolin Chen To: , , CC: , , , , , , , , Subject: [PATCH v1 14/14] iommu/arm-smmu-v3: Add arm_smmu_cache_invalidate_user Date: Thu, 9 Mar 2023 02:53:50 -0800 Message-ID: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF000108EB:EE_|CH2PR12MB4213:EE_ X-MS-Office365-Filtering-Correlation-Id: 707da11f-994c-464f-4114-08db208cb91f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: VNxCBgug5Qm10VaMVAHqAoU6X5M/+cDj7TjdChldMWsHNo/Zpta018FEGS9eXf5E/Wt2BBVIEOh/GdrkvpjE7PVXukYF2uf2fo9YTjMKRpVQ/0xleADGVlkNoh+SYy4XaqjmWCpDSTP9z4wexw5Os5+9SRiUZPgU1J8Ansvv7ow+z9IdfAw1/Rppq4hWdPEsYXKrhptwtvcGA4T03+VtumbgFP8mcq7fT0V5eIYnaMExcjXs/m2L+gvbQ4CJVL0y0a1gbuEn4l5MXwyQtQYZ/sibn61d+1wE3nvCwQi5Kqy3V991YyjVOkFgaKe3upyneWz9GkkUUs8VT+dcnPmsWHqWACA8boJfHGeI7n+kmGHlrDA7YhLPDztEEbsTpp3pjtesErJ7lxFkUQ3G6kGbmK3l3IWLN83+AGNSwRVZa9xZF6pvJgtL3qabwAZfHARtc7+Yz85B1d9yg21ih2P0TaIHPTiKcyDfCDKcV4+GkjX/0odwhk4OBVjOFT53mn/Zm0uMhj0Dz3vx+268vAOjwz6QV7cDkgFwwmr4pvPAPkMjnX8SBLFIqK78TFOE/okqlpQBt0ajX/5PFY+HNGIFuum8REUjiBEIE/OE/OndThGPjg/3BRRYLu+SvoS/ObcK/NsKa+vin8qlsUNbp2Lc+wpj5b9p+6yPkCcoLy/3yvUfNpv58neVf2E/9fb+geOssubSWzLRfFcC/UdCV85ce2ZxhjkrGfUTR0JBmksKLdnbdyVLJgnUGUpYfU/Co1AN X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230025)(4636009)(396003)(376002)(346002)(136003)(39860400002)(451199018)(40470700004)(46966006)(36840700001)(40460700003)(36756003)(54906003)(110136005)(478600001)(316002)(7696005)(7416002)(5660300002)(2906002)(8936002)(70206006)(8676002)(70586007)(4326008)(41300700001)(82740400003)(7636003)(36860700001)(40480700001)(356005)(86362001)(6666004)(186003)(2616005)(26005)(83380400001)(82310400005)(336012)(426003)(47076005);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Mar 2023 10:54:57.4525 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 707da11f-994c-464f-4114-08db208cb91f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF000108EB.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4213 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230309_025504_088370_0F628B91 X-CRM114-Status: GOOD ( 14.08 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add arm_smmu_cache_invalidate_user() function for user space to invalidate TLB entries and Context Descriptors, since either an IO page table entrie or a Context Descriptor in the user space is still cached by the hardware. The input user_data is defined in "struct iommu_hwpt_invalidate_arm_smmuv3" that contains the essential data for corresponding invalidation commands. Co-developed-by: Eric Auger Signed-off-by: Eric Auger Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 56 +++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index ac63185ae268..7d73eab5e7f4 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2880,9 +2880,65 @@ static void arm_smmu_remove_dev_pasid(struct device *dev, ioasid_t pasid) arm_smmu_sva_remove_dev_pasid(domain, dev, pasid); } +static void arm_smmu_cache_invalidate_user(struct iommu_domain *domain, + void *user_data) +{ + struct iommu_hwpt_invalidate_arm_smmuv3 *inv_info = user_data; + struct arm_smmu_cmdq_ent cmd = { .opcode = inv_info->opcode }; + struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); + struct arm_smmu_device *smmu = smmu_domain->smmu; + size_t granule_size = inv_info->granule_size; + unsigned long iova = 0; + size_t size = 0; + int ssid = 0; + + if (!smmu || !smmu_domain->s2 || domain->type != IOMMU_DOMAIN_NESTED) + return; + + switch (inv_info->opcode) { + case CMDQ_OP_CFGI_CD: + case CMDQ_OP_CFGI_CD_ALL: + return arm_smmu_sync_cd(smmu_domain, inv_info->ssid, true); + case CMDQ_OP_TLBI_NH_VA: + cmd.tlbi.asid = inv_info->asid; + fallthrough; + case CMDQ_OP_TLBI_NH_VAA: + if (!granule_size || !(granule_size & smmu->pgsize_bitmap) || + granule_size & ~(1ULL << __ffs(granule_size))) + return; + + iova = inv_info->range.start; + size = inv_info->range.last - inv_info->range.start + 1; + if (!size) + return; + + cmd.tlbi.vmid = smmu_domain->s2->s2_cfg.vmid; + cmd.tlbi.leaf = inv_info->flags & IOMMU_SMMUV3_CMDQ_TLBI_VA_LEAF; + __arm_smmu_tlb_inv_range(&cmd, iova, size, granule_size, smmu_domain); + break; + case CMDQ_OP_TLBI_NH_ASID: + cmd.tlbi.asid = inv_info->asid; + fallthrough; + case CMDQ_OP_TLBI_NH_ALL: + cmd.tlbi.vmid = smmu_domain->s2->s2_cfg.vmid; + arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); + break; + case CMDQ_OP_ATC_INV: + ssid = inv_info->ssid; + iova = inv_info->range.start; + size = inv_info->range.last - inv_info->range.start + 1; + break; + default: + return; + } + + arm_smmu_atc_inv_domain(smmu_domain, ssid, iova, size); +} + static const struct iommu_domain_ops arm_smmu_nested_domain_ops = { .attach_dev = arm_smmu_attach_dev, .free = arm_smmu_domain_free, + .cache_invalidate_user = arm_smmu_cache_invalidate_user, }; static struct iommu_domain *