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Sun, 28 Jul 2024 15:45:03 -0700 From: Nicolin Chen To: CC: , , , , , , , , , Subject: [PATCH v10 3/9] iommu/arm-smmu-v3: Pass in cmdq pointer to arm_smmu_cmdq_build_sync_cmd Date: Sun, 28 Jul 2024 15:44:48 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000A6731:EE_|DS0PR12MB7510:EE_ X-MS-Office365-Filtering-Correlation-Id: 2304aece-2ab9-4861-c1e4-08dcaf56f16d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: fdJpCxYZYJsbM9pSjsLPoiPnHdudgJBitZRibOYd4z/Dm0oMn7cB5AV5Szh0y92S34k9QwZwrXk1H8CqeFCo4CphGGj3agM7heUnerd53lFURLMIUyb3t2DWod63nEElpriOevfiOZdQgoQ3h5S1m4ifgQ09I6f2GRqnfSMBcLmp3QoNiKxKZf02BwJDI1oD37zE25H29w5kSYUJEjlJMP2GyXWsNG7zd3eUOIp49tZ83orF2YpbzPJOj8hgh7ucJD9MdMYuqHOXWnZupsRfAGwM/+a2yYqsNhtmE3OwkWspXGjKi3byYNntjXBjCSYRF4Fxf6+epQxgSJVsB0KG6GbjNIa1LoPPdB6xt2rOlCL8eLLqqPky7Uc9Zr0w+dnwOIMoBiJlw9Q7YCdD7oZtXT55NvFiVK1winLK6FmnVY42pVctY0APu0wLlRJBmOSdw9DPwufW69hQyDSX6Vz6kssN+KbhtWlVBw7MWNtnhl5KFJtiM0lIOonyocd2b1yhgG2oeLWSqx9uak1dUAVdVSdtmU/8+V1oUoefGlFzQJhZkgCQ1YP2bGx6owlQLvZGJ0P0cwzHJI+ypWH/Z8KzKM4qt4zJC7h98ssvCYYioFNyoqJBjEEDg+tg3Jv2AXxyp5hnp99KK3P11NYTN/QkTffP5olLYD6Wy14ttOcF6DiZHXSK6CCwqrnhQBHIC4D2df1dVa4fp8Q/ukJvvhELKatC1BOEJmfdFOIm1CRM2SBhhKAVJ4eNp2oXZkVcCyNcyhNfHCAlY4c/6VdTFH0jC3EZS18qdnyxCk8iQ/xpmIEHvq2HVacHSh/YGFiOAqU5ih57dfALIcXnB+aYZ2mOM3J0DVhD+pI02lfUk8Qh50W3MxvCE2FHPoE4LxFQMrBxtRQlaqml4veIZx8LvP2Nf9w4hBc+JdM50bdqgjJgqgWwbFgLGLxTmVjtW0I9w79TWH6uc/pVsvWR4asQedeyiISqPmwFtTcVnFQkiaNhZcO8s4MG72IrIV2N/zL8Zxmid9t8AmZjXKZ0rcQPCrHC8xeBSDu/IBwoInJ0W9ZJ4EQvURyHafQzQXusHxGvwPbxNe3IOMvTbDNOFKCF1KOyezAvYmbTQccD3LAYeXHPuQFz1AQXylzqVgCbzYavZuE5oe1Aearui3YcpSoTSDjR7x3oAjjmgRDfGGiFXUztMUGR8SwHYG08UDl1n8ypeMg4fxM+f0dXdBGczkgG9AoRDIvBEOyW1XpQ9HIUi/kOKT+6jGCkpTKo04ExwuAz/tTID3B90Kzg8eBNNshj4O7il1luUpLyWMq/B5O5iISwcXSwbQjKFDUUvEO7minn2ZtpEdHkIp4KO0Ae3kUwYrHjThkP0PI6p5tCEgZ7u+W5A/0dOXN+XCQldMODEMM6Irznfcv8hkAqiue9LxYc9aCYNuLfRoexFn0Q3nWitw3VOZ9dlgixo2YBBPB49iTJ48nh X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(376014)(82310400026)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Jul 2024 22:45:13.1380 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2304aece-2ab9-4861-c1e4-08dcaf56f16d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000A6731.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7510 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240728_154519_781822_585CF455 X-CRM114-Status: GOOD ( 12.35 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The CMDQV extension on NVIDIA Tegra241 SoC only supports CS_NONE in the CS field of CMD_SYNC, v.s. standard SMMU CMDQ. Pass in the cmdq pointer directly, so the function can identify a different cmdq implementation. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index f481d7be3d4ec..d11362e9fc8a0 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -342,8 +342,10 @@ static struct arm_smmu_cmdq *arm_smmu_get_cmdq(struct arm_smmu_device *smmu) } static void arm_smmu_cmdq_build_sync_cmd(u64 *cmd, struct arm_smmu_device *smmu, - struct arm_smmu_queue *q, u32 prod) + struct arm_smmu_cmdq *cmdq, u32 prod) { + struct arm_smmu_queue *q = &cmdq->q; + cmd[1] = 0; cmd[0] = FIELD_PREP(CMDQ_0_OP, CMDQ_OP_CMD_SYNC) | FIELD_PREP(CMDQ_SYNC_0_MSH, ARM_SMMU_SH_ISH) | @@ -364,7 +366,7 @@ static void arm_smmu_cmdq_build_sync_cmd(u64 *cmd, struct arm_smmu_device *smmu, } static void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu, - struct arm_smmu_queue *q) + struct arm_smmu_cmdq *cmdq) { static const char * const cerror_str[] = { [CMDQ_ERR_CERROR_NONE_IDX] = "No error", @@ -372,6 +374,7 @@ static void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu, [CMDQ_ERR_CERROR_ABT_IDX] = "Abort on command fetch", [CMDQ_ERR_CERROR_ATC_INV_IDX] = "ATC invalidate timeout", }; + struct arm_smmu_queue *q = &cmdq->q; int i; u64 cmd[CMDQ_ENT_DWORDS]; @@ -410,14 +413,14 @@ static void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu, dev_err(smmu->dev, "\t0x%016llx\n", (unsigned long long)cmd[i]); /* Convert the erroneous command into a CMD_SYNC */ - arm_smmu_cmdq_build_sync_cmd(cmd, smmu, q, cons); + arm_smmu_cmdq_build_sync_cmd(cmd, smmu, cmdq, cons); queue_write(Q_ENT(q, cons), cmd, q->ent_dwords); } static void arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu) { - __arm_smmu_cmdq_skip_err(smmu, &smmu->cmdq.q); + __arm_smmu_cmdq_skip_err(smmu, &smmu->cmdq); } /* @@ -780,7 +783,7 @@ static int arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu, arm_smmu_cmdq_write_entries(cmdq, cmds, llq.prod, n); if (sync) { prod = queue_inc_prod_n(&llq, n); - arm_smmu_cmdq_build_sync_cmd(cmd_sync, smmu, &cmdq->q, prod); + arm_smmu_cmdq_build_sync_cmd(cmd_sync, smmu, cmdq, prod); queue_write(Q_ENT(&cmdq->q, prod), cmd_sync, CMDQ_ENT_DWORDS); /*