From patchwork Mon Jun 6 15:25:36 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 852372 Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by demeter2.kernel.org (8.14.4/8.14.3) with ESMTP id p56FQ27R012068 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Mon, 6 Jun 2011 15:26:24 GMT Received: from canuck.infradead.org ([2001:4978:20e::1]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QTbgf-0007ve-2L; Mon, 06 Jun 2011 15:25:53 +0000 Received: from localhost ([127.0.0.1] helo=canuck.infradead.org) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1QTbge-0007gM-LF; Mon, 06 Jun 2011 15:25:52 +0000 Received: from galois.linutronix.de ([2001:470:1f0b:1c35:abcd:42:0:1]) by canuck.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QTbgV-0007g3-IY for linux-arm-kernel@lists.infradead.org; Mon, 06 Jun 2011 15:25:50 +0000 Received: from localhost ([127.0.0.1]) by Galois.linutronix.de with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1QTbgP-0005Qo-Fc; Mon, 06 Jun 2011 17:25:37 +0200 Date: Mon, 6 Jun 2011 17:25:36 +0200 (CEST) From: Thomas Gleixner To: Holger Freyther Subject: Re: TI-Davinci 6446 oops on interrupts In-Reply-To: <4DECEDF9.4010202@selfish.org> Message-ID: References: <4DECCADE.6080100@selfish.org> <4DECD8C0.6010908@freyther.de> <4DECEDF9.4010202@selfish.org> User-Agent: Alpine 2.02 (LFD 1266 2009-07-14) MIME-Version: 1.0 X-Linutronix-Spam-Score: -1.0 X-Linutronix-Spam-Level: - X-Linutronix-Spam-Status: No , -1.0 points, 5.0 required, ALL_TRUSTED=-1, SHORTCIRCUIT=-0.0001 X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20110606_112549_706182_8D311B4A X-CRM114-Status: GOOD ( 16.71 ) X-Spam-Score: -0.0 (/) X-Spam-Report: SpamAssassin version 3.3.1 on canuck.infradead.org summary: Content analysis details: (-0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 T_RP_MATCHES_RCVD Envelope sender domain matches handover relay domain Cc: Kevin Hilman , linux-arm-kernel X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter2.kernel.org [140.211.167.43]); Mon, 06 Jun 2011 15:26:24 +0000 (UTC) On Mon, 6 Jun 2011, Holger Freyther wrote: > On 06/06/2011 04:54 PM, Thomas Gleixner wrote: > > and both interrupts should be on REG1.. so for IRQ56 it looks like this method > is entered with bogus data. Again, I have no idea about the underlying code, > but could there be an issue with chained irq and the GC IRC code? Crap, yes. The code which does the chained handler setup overwrites chip_data. Subject: arm: davinci: Fix fallout from generic irq chip conversion From: Thomas Gleixner Date: Mon, 06 Jun 2011 11:51:43 +0200 Signed-off-by: Thomas Gleixner Tested-by: Holger Hans Peter Freyther --- arch/arm/mach-davinci/gpio.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) Index: linux-2.6/arch/arm/mach-davinci/gpio.c =================================================================== --- linux-2.6.orig/arch/arm/mach-davinci/gpio.c +++ linux-2.6/arch/arm/mach-davinci/gpio.c @@ -252,9 +252,11 @@ static struct irq_chip gpio_irqchip = { static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) { - struct davinci_gpio_regs __iomem *g = irq2regs(irq); + struct davinci_gpio_regs __iomem *g; u32 mask = 0xffff; + g = (__force struct davinci_gpio_regs __iomem *) irq_desc_get_handler_data(desc); + /* we only care about one bank */ if (irq & 1) mask <<= 16; @@ -422,8 +424,7 @@ static int __init davinci_gpio_irq_setup /* set up all irqs in this bank */ irq_set_chained_handler(bank_irq, gpio_irq_handler); - irq_set_chip_data(bank_irq, (__force void *)g); - irq_set_handler_data(bank_irq, (void *)irq); + irq_set_handler_data(bank_irq, (__force void *)g); for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) { irq_set_chip(irq, &gpio_irqchip);