From patchwork Sat Oct 6 01:32:09 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolas Pitre X-Patchwork-Id: 1556421 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id C84DBDF24C for ; Sat, 6 Oct 2012 01:35:30 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TKJFb-00016V-Hk; Sat, 06 Oct 2012 01:32:19 +0000 Received: from mail-qc0-f177.google.com ([209.85.216.177]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1TKJFX-00016H-La for linux-arm-kernel@lists.infradead.org; Sat, 06 Oct 2012 01:32:16 +0000 Received: by mail-qc0-f177.google.com with SMTP id u28so1665918qcs.36 for ; Fri, 05 Oct 2012 18:32:11 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=date:from:to:cc:subject:in-reply-to:message-id:references :user-agent:mime-version:content-type:x-gm-message-state; bh=XkCXzydv7CatHsUa3tKgyAMSVU3kk4gnTFG+V1l0QzM=; b=hNoBBXJFgsdoNKvQq4W1A8aMGYrumYVI3alf9ul0p3/D3DEnUbbDQwoFSCAq+QcT0e dEKDCgmHHryz3T0R2L+yjXHHlapBiu/x4sfPvqaNC7qBsrjucHuAtsKaCwFLDxYCW205 NfDoLOz7PtDwh37yAJi5er+XouFDmakvdjIbvOlEnUJM7OCbfkH3KbtRsCuza5kHtkTE TJLwcaARsc8yGHhyW7gOe07HmeHEFP+Asy/kzElDpt3SoXDL7aMBZ1NVN2VU8fPZ6KRm AJdjlDhmkzNoyTTOQEYb2MVdk/lYr9+pBpaa/amMoOW+QO7h0Z2wk9vMZSccYmIHCmhR SeGA== Received: by 10.224.191.130 with SMTP id dm2mr19512516qab.98.1349487131470; Fri, 05 Oct 2012 18:32:11 -0700 (PDT) Received: from xanadu.home (modemcable203.213-202-24.mc.videotron.ca. [24.202.213.203]) by mx.google.com with ESMTPS id c9sm11543268qeh.1.2012.10.05.18.32.10 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 05 Oct 2012 18:32:10 -0700 (PDT) Date: Fri, 5 Oct 2012 21:32:09 -0400 (EDT) From: Nicolas Pitre To: Tony Lindgren Subject: Re: [PATCH v2 2/7] ARM: virt: allow the kernel to be entered in HYP mode In-Reply-To: <20121005235046.GW3874@atomide.com> Message-ID: References: <1347036934-8519-1-git-send-email-marc.zyngier@arm.com> <1347036934-8519-3-git-send-email-marc.zyngier@arm.com> <20121005200822.GQ3874@atomide.com> <20121005230908.GC15246@n2100.arm.linux.org.uk> <20121005232325.GV3874@atomide.com> <20121005235046.GW3874@atomide.com> User-Agent: Alpine 2.02 (LFD 1266 2009-07-14) MIME-Version: 1.0 X-Gm-Message-State: ALoCoQm2udr8xCZO28as5nTGXGzQmeLgS5ALMWK4LYDtLhnJ8B4tVdJFPJ04dk6YgfD0NG3Dekg7 X-Spam-Note: CRM114 invocation failed X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.216.177 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Marc Zyngier , Dave Martin , linux-omap@vger.kernel.org, Russell King - ARM Linux , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org On Fri, 5 Oct 2012, Tony Lindgren wrote: > * Tony Lindgren [121005 16:27]: > > * Russell King - ARM Linux [121005 16:10]: > > > On Fri, Oct 05, 2012 at 01:08:22PM -0700, Tony Lindgren wrote: > > > > Just bisected this down in linux-next for breaking booting of > > > > my omap2420 ARMv6 based n8x0.. > > > > > > > > > --- a/arch/arm/kernel/head.S > > > > > +++ b/arch/arm/kernel/head.S > > > > > @@ -83,8 +83,12 @@ ENTRY(stext) > > > > > THUMB( .thumb ) @ switch to Thumb now. > > > > > THUMB(1: ) > > > > > > > > > > - setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode > > > > > - @ and irqs disabled > > > > > +#ifdef CONFIG_ARM_VIRT_EXT > > > > > + bl __hyp_stub_install > > > > > +#endif > > > > > + @ ensure svc mode and all interrupts masked > > > > > + safe_svcmode_maskall r9 > > > > > + > > > > > mrc p15, 0, r9, c0, c0 @ get processor id > > > > > bl __lookup_processor_type @ r5=procinfo r9=cpuid > > > > > movs r10, r5 @ invalid processor (r5=0)? > > > > > > > > ..and looks like undoing this part fixes it. Any ideas? > > > > > > > > I quickly tried disabling ARCH_OMAP3 and ARCH_OMAP4 so it's > > > > ARMv6 but that does not help. > > The same kernel boots on 2430sdp, which is the same ARMv6 core > as 2430 if I remember correctly. So this hints that it has something > to do with the bits set differently by the bootloader? Possibly. What if you apply this on top: Nicolas diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h index 683a1e6b60..b276c26e19 100644 --- a/arch/arm/include/asm/assembler.h +++ b/arch/arm/include/asm/assembler.h @@ -254,8 +254,7 @@ mov lr , \reg and lr , lr , #MODE_MASK cmp lr , #HYP_MODE - orr \reg , \reg , #PSR_A_BIT | PSR_I_BIT | PSR_F_BIT - bic \reg , \reg , #MODE_MASK + mov \reg , #PSR_A_BIT | PSR_I_BIT | PSR_F_BIT orr \reg , \reg , #SVC_MODE THUMB( orr \reg , \reg , #PSR_T_BIT ) msr spsr_cxsf, \reg