From patchwork Sat Oct 6 14:06:00 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolas Pitre X-Patchwork-Id: 1557811 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id 9DB543FD56 for ; Sat, 6 Oct 2012 14:08:54 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TKV16-0001o2-PF; Sat, 06 Oct 2012 14:06:08 +0000 Received: from mail-qc0-f177.google.com ([209.85.216.177]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1TKV12-0001no-HO for linux-arm-kernel@lists.infradead.org; Sat, 06 Oct 2012 14:06:05 +0000 Received: by mail-qc0-f177.google.com with SMTP id u28so1920880qcs.36 for ; Sat, 06 Oct 2012 07:06:02 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=date:from:to:cc:subject:in-reply-to:message-id:references :user-agent:mime-version:content-type:x-gm-message-state; bh=TrLDObqkl3TCbyozTBBpE+JQfIo0RjKPA28/b11caw0=; b=kWIFmlqnTgE4+38LuC4FLi3aPnW1OG6iEui9vkMqDNJaXMvJyNzbg2rLd9PQjll9Vt jcu1083Z+w1nqPiJMa2prhZIflcNcYDYkGv1/6Dyl1ERP9qVMnGP4PWl+9mS6wDwBtgI lABFWrETHKA6wTm4IKIpYAUhU265eWUWE1TKSut6pihdlVzIyizXXd4uvJGlYK6C3yU2 E+CTcmsWgH0lB0CEbvTjZJLezjeoH76KVYMTjxxlsZj07Quzq4TMc+NCKcbRVOr9Ri0w NqokpkkykSVhvjTD4ugNnLarIUahLaT92b9aQErCbNTg3mEiFZSCNe+L5F18smfTgEC5 AdmA== Received: by 10.224.78.197 with SMTP id m5mr21741669qak.36.1349532362722; Sat, 06 Oct 2012 07:06:02 -0700 (PDT) Received: from xanadu.home (modemcable203.213-202-24.mc.videotron.ca. [24.202.213.203]) by mx.google.com with ESMTPS id gd19sm12729166qeb.0.2012.10.06.07.06.01 (version=TLSv1/SSLv3 cipher=OTHER); Sat, 06 Oct 2012 07:06:01 -0700 (PDT) Date: Sat, 6 Oct 2012 10:06:00 -0400 (EDT) From: Nicolas Pitre To: Marc Zyngier Subject: Re: [PATCH v2 2/7] ARM: virt: allow the kernel to be entered in HYP mode In-Reply-To: <6d3553bfe8a2d1ac88cab852100616a7@localhost> Message-ID: References: <1347036934-8519-1-git-send-email-marc.zyngier@arm.com> <1347036934-8519-3-git-send-email-marc.zyngier@arm.com> <20121005200822.GQ3874@atomide.com> <6d3553bfe8a2d1ac88cab852100616a7@localhost> User-Agent: Alpine 2.02 (LFD 1266 2009-07-14) MIME-Version: 1.0 X-Gm-Message-State: ALoCoQnaT5uiBQppHsvWTAqLE5WZuALh4QHbHNn6slq+40XOn9eK5Mq0u0pHtBo49/rhFA7HXQZX X-Spam-Note: CRM114 invocation failed X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.216.177 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Tony Lindgren , Dave Martin , linux-omap@vger.kernel.org, Russell King - ARM Linux , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org On Sat, 6 Oct 2012, Marc Zyngier wrote: > Hi Tony, > > On Fri, 5 Oct 2012 13:08:22 -0700, Tony Lindgren wrote: > > Hi, > > > > * Marc Zyngier [120907 10:04]: > >> From: Dave Martin > >> > >> This patch does two things: > >> > >> * Ensure that asynchronous aborts are masked at kernel entry. > >> The bootloader should be masking these anyway, but this reduces > >> the damage window just in case it doesn't. > >> > >> * Enter svc mode via exception return to ensure that CPU state is > >> properly serialised. This does not matter when switching from > >> an ordinary privileged mode ("PL1" modes in ARMv7-AR rev C > >> parlance), but it potentially does matter when switching from a > >> another privileged mode such as hyp mode. > >> > >> This should allow the kernel to boot safely either from svc mode or > >> hyp mode, even if no support for use of the ARM Virtualization > >> Extensions is built into the kernel. > >> > >> Signed-off-by: Dave Martin > >> Signed-off-by: Marc Zyngier > > > > Just bisected this down in linux-next for breaking booting of > > my omap2420 ARMv6 based n8x0.. > > > >> --- a/arch/arm/kernel/head.S > >> +++ b/arch/arm/kernel/head.S > >> @@ -83,8 +83,12 @@ ENTRY(stext) > >> THUMB( .thumb ) @ switch to Thumb now. > >> THUMB(1: ) > >> > >> - setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode > >> - @ and irqs disabled > >> +#ifdef CONFIG_ARM_VIRT_EXT > >> + bl __hyp_stub_install > >> +#endif > >> + @ ensure svc mode and all interrupts masked > >> + safe_svcmode_maskall r9 > >> + > >> mrc p15, 0, r9, c0, c0 @ get processor id > >> bl __lookup_processor_type @ r5=procinfo r9=cpuid > >> movs r10, r5 @ invalid processor (r5=0)? > > > > ..and looks like undoing this part fixes it. Any ideas? > > > > I quickly tried disabling ARCH_OMAP3 and ARCH_OMAP4 so it's > > ARMv6 but that does not help. > > If you compiled for v6 only, we can safely exclude __hyp_stub_install, and > I assume that you get past the decompressor. > > If so, that indicates some side effect of the safe_svcmode_maskall macro, > and I suspect the "movs pc, lr" bit. That would be surprizing if the "movs pc, lr" was to blame. This should work on all architectures. However the A bit might be to blame. > Can you try the attached patch? It basically falls back to the previous > behaviour if not entered in HYP mode. This is likely to work of course. However I think we should try to pinpoint the exact problem i.e. whether it is the A bit or the "movs pc, lr" which makes a difference (it is unlikely to be both). So I was about to suggest to test this patch as well: Nicolas diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h index 683a1e6b60..118e22ee46 100644 --- a/arch/arm/include/asm/assembler.h +++ b/arch/arm/include/asm/assembler.h @@ -254,8 +254,7 @@ mov lr , \reg and lr , lr , #MODE_MASK cmp lr , #HYP_MODE - orr \reg , \reg , #PSR_A_BIT | PSR_I_BIT | PSR_F_BIT - bic \reg , \reg , #MODE_MASK + mov \reg , #PSR_I_BIT | PSR_F_BIT orr \reg , \reg , #SVC_MODE THUMB( orr \reg , \reg , #PSR_T_BIT ) msr spsr_cxsf, \reg