From patchwork Fri May 3 14:09:46 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 2517301 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) by patchwork1.kernel.org (Postfix) with ESMTP id CC59B3FCA5 for ; Fri, 3 May 2013 14:10:53 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UYGh4-0006pn-2I; Fri, 03 May 2013 14:10:38 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UYGgu-00005s-Fh; Fri, 03 May 2013 14:10:28 +0000 Received: from galois.linutronix.de ([2001:470:1f0b:db:abcd:42:0:1]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UYGgn-0008VB-RX for linux-arm-kernel@lists.infradead.org; Fri, 03 May 2013 14:10:25 +0000 Received: from localhost ([127.0.0.1]) by Galois.linutronix.de with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1UYGgF-0004Cg-Gc; Fri, 03 May 2013 16:09:47 +0200 Date: Fri, 3 May 2013 16:09:46 +0200 (CEST) From: Thomas Gleixner To: Sebastian Hesselbarth Subject: Re: [PATCH v2 1/5] irqchip: add support for Marvell Orion SoCs In-Reply-To: <5183B7ED.7030800@gmail.com> Message-ID: References: <1367519104-19677-1-git-send-email-sebastian.hesselbarth@gmail.com> <1367538519-23940-1-git-send-email-sebastian.hesselbarth@gmail.com> <1367538519-23940-2-git-send-email-sebastian.hesselbarth@gmail.com> <20130503125527.GE18614@n2100.arm.linux.org.uk> <5183B7ED.7030800@gmail.com> User-Agent: Alpine 2.02 (LFD 1266 2009-07-14) MIME-Version: 1.0 X-Linutronix-Spam-Score: -1.0 X-Linutronix-Spam-Level: - X-Linutronix-Spam-Status: No , -1.0 points, 5.0 required, ALL_TRUSTED=-1, SHORTCIRCUIT=-0.0001 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130503_101022_325983_881E27AE X-CRM114-Status: GOOD ( 24.28 ) X-Spam-Score: -4.5 (----) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-4.5 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.6 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Thomas Petazzoni , Andrew Lunn , Russell King - ARM Linux , Jason Cooper , Arnd Bergmann , Jean-Francois Moine , devicetree-discuss@lists.ozlabs.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , Jason Gunthorpe , Gregory Clement , Rob Landley , Grant Likely , Ezequiel Garcia , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org On Fri, 3 May 2013, Sebastian Hesselbarth wrote: > On 05/03/13 14:55, Russell King - ARM Linux wrote: > > This is where it starts to get tricky, because I can't see how you'd > > merge the irq_alloc_generic_chip() and irq_setup_generic_chip() with > > this. Maybe you don't need to do anything here and just do all that > > in orion_of_init() instead? But then you seem to need to know the > > virq range before hand, and I can't see how that's known. Maybe Thomas > > can provide some enlightenment about how the gc irqchip stuff works > > with the irq domain stuff... > > Exactly, and that is what I am looking into right now. But hell, I am > not an expert in linux irq yet. Moreover, I am not even sure if it is > okay to rely on irqdomain or at least irq_data->hw_irq at all. Here is a solution to that problem. 1) It adds a mask field to irq_data so we dont have to compute the mask over and over 2) For compability with existing users it populates the mask with 1 << (d->irq - gc->irq_base) 3) It gives you the option to disable that mask setup or let it generate from d->hwirq I'm still looking into a way how to proper support the generic chip / linear domain mapping in the setup path. Will send you a draft patch to play with later. Thanks, tglx Index: linux-2.6/include/linux/irq.h =================================================================== --- linux-2.6.orig/include/linux/irq.h +++ linux-2.6/include/linux/irq.h @@ -119,6 +119,7 @@ struct irq_domain; /** * struct irq_data - per irq and irq chip data passed down to chip functions + * @mask: precomputed bitmask for accessing the chip registers * @irq: interrupt number * @hwirq: hardware interrupt number, local to the interrupt domain * @node: node index useful for balancing @@ -138,6 +139,7 @@ struct irq_domain; * irq_data. */ struct irq_data { + u32 mask; unsigned int irq; unsigned long hwirq; unsigned int node; @@ -700,10 +702,14 @@ struct irq_chip_generic { * @IRQ_GC_INIT_NESTED_LOCK: Set the lock class of the irqs to nested for * irq chips which need to call irq_set_wake() on * the parent irq. Usually GPIO implementations + * @IRQ_GC_NO_MASK: Do not calculate irq_data->mask + * @IRQ_GC_MASK_FROM_HWIRQ: Calculate irq_data->mask from the hwirq number */ enum irq_gc_flags { IRQ_GC_INIT_MASK_CACHE = 1 << 0, IRQ_GC_INIT_NESTED_LOCK = 1 << 1, + IRQ_GC_NO_MASK = 1 << 2, + IRQ_GC_MASK_FROM_HWIRQ = 1 << 4, }; /* Generic chip callback functions */ Index: linux-2.6/kernel/irq/generic-chip.c =================================================================== --- linux-2.6.orig/kernel/irq/generic-chip.c +++ linux-2.6/kernel/irq/generic-chip.c @@ -39,7 +39,7 @@ void irq_gc_noop(struct irq_data *d) void irq_gc_mask_disable_reg(struct irq_data *d) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); - u32 mask = 1 << (d->irq - gc->irq_base); + u32 mask = d->mask; irq_gc_lock(gc); irq_reg_writel(mask, gc->reg_base + cur_regs(d)->disable); @@ -57,7 +57,7 @@ void irq_gc_mask_disable_reg(struct irq_ void irq_gc_mask_set_bit(struct irq_data *d) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); - u32 mask = 1 << (d->irq - gc->irq_base); + u32 mask = d->mask; irq_gc_lock(gc); gc->mask_cache |= mask; @@ -75,7 +75,7 @@ void irq_gc_mask_set_bit(struct irq_data void irq_gc_mask_clr_bit(struct irq_data *d) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); - u32 mask = 1 << (d->irq - gc->irq_base); + u32 mask = d->mask; irq_gc_lock(gc); gc->mask_cache &= ~mask; @@ -93,7 +93,7 @@ void irq_gc_mask_clr_bit(struct irq_data void irq_gc_unmask_enable_reg(struct irq_data *d) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); - u32 mask = 1 << (d->irq - gc->irq_base); + u32 mask = d->mask; irq_gc_lock(gc); irq_reg_writel(mask, gc->reg_base + cur_regs(d)->enable); @@ -108,7 +108,7 @@ void irq_gc_unmask_enable_reg(struct irq void irq_gc_ack_set_bit(struct irq_data *d) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); - u32 mask = 1 << (d->irq - gc->irq_base); + u32 mask = d->mask; irq_gc_lock(gc); irq_reg_writel(mask, gc->reg_base + cur_regs(d)->ack); @@ -122,7 +122,7 @@ void irq_gc_ack_set_bit(struct irq_data void irq_gc_ack_clr_bit(struct irq_data *d) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); - u32 mask = ~(1 << (d->irq - gc->irq_base)); + u32 mask = ~d->mask; irq_gc_lock(gc); irq_reg_writel(mask, gc->reg_base + cur_regs(d)->ack); @@ -136,7 +136,7 @@ void irq_gc_ack_clr_bit(struct irq_data void irq_gc_mask_disable_reg_and_ack(struct irq_data *d) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); - u32 mask = 1 << (d->irq - gc->irq_base); + u32 mask = d->mask; irq_gc_lock(gc); irq_reg_writel(mask, gc->reg_base + cur_regs(d)->mask); @@ -151,7 +151,7 @@ void irq_gc_mask_disable_reg_and_ack(str void irq_gc_eoi(struct irq_data *d) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); - u32 mask = 1 << (d->irq - gc->irq_base); + u32 mask = d->mask; irq_gc_lock(gc); irq_reg_writel(mask, gc->reg_base + cur_regs(d)->eoi); @@ -169,7 +169,7 @@ void irq_gc_eoi(struct irq_data *d) int irq_gc_set_wake(struct irq_data *d, unsigned int on) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); - u32 mask = 1 << (d->irq - gc->irq_base); + u32 mask = d->mask; if (!(mask & gc->wake_enabled)) return -EINVAL; @@ -254,6 +254,15 @@ void irq_setup_generic_chip(struct irq_c if (flags & IRQ_GC_INIT_NESTED_LOCK) irq_set_lockdep_class(i, &irq_nested_lock_class); + if (!(flags & IRQ_GC_NO_MASK)) { + struct irq_data *d = irq_get_irq_data(i); + u32 mask; + + if (flags & IRQ_GC_MASK_FROM_HWIRQ) + d->mask = 1 << (d->hwirq % 32); + else + d->mask = 1 << (i - gc->irq_base); + } irq_set_chip_and_handler(i, &ct->chip, ct->handler); irq_set_chip_data(i, gc); irq_modify_status(i, clr, set);