From patchwork Thu Jul 18 17:24:48 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolas Pitre X-Patchwork-Id: 2829742 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 6007E9F967 for ; Thu, 18 Jul 2013 17:25:58 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E41C0201ED for ; Thu, 18 Jul 2013 17:25:56 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8D2A6201E9 for ; Thu, 18 Jul 2013 17:25:55 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UzrxH-0002Jg-9z; Thu, 18 Jul 2013 17:25:27 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Uzrx5-0008Rg-GG; Thu, 18 Jul 2013 17:25:15 +0000 Received: from mail-qe0-f46.google.com ([209.85.128.46]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Uzrx2-0008QZ-1v for linux-arm-kernel@lists.infradead.org; Thu, 18 Jul 2013 17:25:13 +0000 Received: by mail-qe0-f46.google.com with SMTP id nd7so1933249qeb.33 for ; Thu, 18 Jul 2013 10:24:50 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=date:from:to:cc:subject:in-reply-to:message-id:references :user-agent:mime-version:content-type:x-gm-message-state; bh=5/mUfiB6mwVcbkhwZ1HTLOtsSwEcbY6ajGK5NWmr7Ak=; b=XJGh3grB5mG9rP3xgSAHeFd/zyEOeRL666R40XdPwmn661qaHUjHJGSsRyNd2wCqsi jhOr41dxymvcPwmPsXOkkDhiFZR7s4meJjcaFbQgKsuI5i+akZ9ZhXzaV70Vk4UpcoZe zFqq0htb3holaRVqQwbuEXy5TQp0nNrIYci9jgkU0+ig7OxDs9MZrdhLiXkR91MLuELw swbQd2qQsz3y93e3fIGPlPX5DVU9miMmqUv2HckMmPjROtZnq5xWXo16G5UpURFrXzbK JPAwnRahX7rip56DIKrhA/g4kDu8UFFU+LG3Btw92a9cF4QIg1E6LxzouoQspMFXs68r 2yOQ== X-Received: by 10.49.132.69 with SMTP id os5mr13867403qeb.48.1374168290416; Thu, 18 Jul 2013 10:24:50 -0700 (PDT) Received: from xanadu.home (modemcable044.209-83-70.mc.videotron.ca. [70.83.209.44]) by mx.google.com with ESMTPSA id d7sm16181720qag.13.2013.07.18.10.24.49 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 18 Jul 2013 10:24:49 -0700 (PDT) Date: Thu, 18 Jul 2013 13:24:48 -0400 (EDT) From: Nicolas Pitre To: Dave Martin , Russell King - ARM Linux Subject: Re: [PATCH 1/4] ARM: vexpress/dcscb: fix cache disabling sequences In-Reply-To: <20130718150408.GB2655@localhost.localdomain> Message-ID: References: <1374118116-16836-1-git-send-email-nicolas.pitre@linaro.org> <1374118116-16836-2-git-send-email-nicolas.pitre@linaro.org> <20130718150408.GB2655@localhost.localdomain> User-Agent: Alpine 2.03 (LFD 1266 2009-07-14) MIME-Version: 1.0 X-Gm-Message-State: ALoCoQnInl74jR8CJJGQHNfnGtVBIi2sHdIPoMGduI71TQpAl1/0DdeCWPbOPmFkX+jjGwVKGEOv X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130718_132512_174813_FDF0B8CB X-CRM114-Status: GOOD ( 29.90 ) X-Spam-Score: -2.6 (--) Cc: Jon Medhurst , lorenzo.pieralisi@arm.com, pawel.moll@arm.com, patches@linaro.org, sudeep.karkadanagesha@arm.com, achin.gupta@arm.com, Olof Johansson , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP [ added Russell for his opinion on the patch below ] On Thu, 18 Jul 2013, Dave Martin wrote: > On Wed, Jul 17, 2013 at 11:28:33PM -0400, Nicolas Pitre wrote: > > Unlike real A15/A7's, the RTSM simulation doesn't appear to hit the > > cache when the CTRL.C bit is cleared. Let's ensure there is no memory > > access within the disable and flush cache sequence, including to the > > stack. > > > > Signed-off-by: Nicolas Pitre > > --- > > arch/arm/mach-vexpress/dcscb.c | 58 +++++++++++++++++++++++++++--------------- > > 1 file changed, 37 insertions(+), 21 deletions(-) > > > > diff --git a/arch/arm/mach-vexpress/dcscb.c b/arch/arm/mach-vexpress/dcscb.c > > index 16d57a8a9d..9f01c04d58 100644 > > --- a/arch/arm/mach-vexpress/dcscb.c > > +++ b/arch/arm/mach-vexpress/dcscb.c > > @@ -136,14 +136,29 @@ static void dcscb_power_down(void) > > /* > > * Flush all cache levels for this cluster. > > * > > - * A15/A7 can hit in the cache with SCTLR.C=0, so we don't need > > - * a preliminary flush here for those CPUs. At least, that's > > - * the theory -- without the extra flush, Linux explodes on > > - * RTSM (to be investigated). > > + * To do so we do: > > + * - Clear the CTLR.C bit to prevent further cache allocations > > SCTLR Fixed. > > + * - Flush the whole cache > > + * - Disable local coherency by clearing the ACTLR "SMP" bit > > + * > > + * Let's do it in the safest possible way i.e. with > > + * no memory access within the following sequence > > + * including the stack. > > */ > > - flush_cache_all(); > > - set_cr(get_cr() & ~CR_C); > > - flush_cache_all(); > > + asm volatile( > > + "mrc p15, 0, r0, c1, c0, 0 @ get CR \n\t" > > + "bic r0, r0, #"__stringify(CR_C)" \n\t" > > + "mcr p15, 0, r0, c1, c0, 0 @ set CR \n\t" > > + "isb \n\t" > > + "bl v7_flush_dcache_all \n\t" > > + "clrex \n\t" > > + "mrc p15, 0, r0, c1, c0, 1 @ get AUXCR \n\t" > > + "bic r0, r0, #(1 << 6) @ disable local coherency \n\t" > > + "mcr p15, 0, r0, c1, c0, 1 @ set AUXCR \n\t" > > + "isb \n\t" > > + "dsb " > > + : : : "r0","r1","r2","r3","r4","r5","r6","r7", > > + "r9","r10","r11","lr","memory"); > > Along with the TC2 support, we now have 4 copies of this code sequence. > > This is basically the A15/A7 native "exit coherency and flash and > disable some levels of dcache" operation, whose only parameter is which > cache levels to flush. > > That's a big mouthful -- we can probably come up with a better name -- > but we've pretty much concluded that there is no way to break this > operation apart into bitesize pieces. Nonetheless, any native > powerdown sequence for these processors will need to do this, or > something closely related. > > Is it worth consolidating, or is that premature? It is probably worth consolidating. What about this: commit 390cf8b9b83eeeebdfef51912f5003a6a9b84115 Author: Nicolas Pitre Date: Thu Jul 18 13:12:48 2013 -0400 ARM: cacheflush: consolidate single-CPU ARMv7 cache disabling code This code is becoming duplicated in many places. So let's consolidate it into a handy macro that is known to be right and available for reuse. Signed-off-by: Nicolas Pitre diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h index 17d0ae8672..8a76933e80 100644 --- a/arch/arm/include/asm/cacheflush.h +++ b/arch/arm/include/asm/cacheflush.h @@ -436,4 +436,33 @@ static inline void __sync_cache_range_r(volatile void *p, size_t size) #define sync_cache_w(ptr) __sync_cache_range_w(ptr, sizeof *(ptr)) #define sync_cache_r(ptr) __sync_cache_range_r(ptr, sizeof *(ptr)) +/* + * Disabling cache access for one CPU in an ARMv7 SMP system is tricky. + * To do so we must: + * + * - Clear the SCTLR.C bit to prevent further cache allocations + * - Flush the desired level of cache + * - Clear the ACTLR "SMP" bit to disable local coherency + * + * ... and so without any intervening memory access in between those steps, + * not even to the stack. + * + * The clobber list is dictated by the call to v7_flush_dcache_*. + */ +#define v7_disable_flush_cache(level) \ + asm volatile( \ + "mrc p15, 0, r0, c1, c0, 0 @ get CR \n\t" \ + "bic r0, r0, #"__stringify(CR_C)" \n\t" \ + "mcr p15, 0, r0, c1, c0, 0 @ set CR \n\t" \ + "isb \n\t" \ + "bl v7_flush_dcache_"__stringify(level)" \n\t" \ + "clrex \n\t" \ + "mrc p15, 0, r0, c1, c0, 1 @ get AUXCR \n\t" \ + "bic r0, r0, #(1 << 6) @ disable local coherency \n\t" \ + "mcr p15, 0, r0, c1, c0, 1 @ set AUXCR \n\t" \ + "isb \n\t" \ + "dsb " \ + : : : "r0","r1","r2","r3","r4","r5","r6","r7", \ + "r9","r10","r11","lr","memory" ) + #endif diff --git a/arch/arm/mach-vexpress/dcscb.c b/arch/arm/mach-vexpress/dcscb.c index 85fffa702f..145d8237d5 100644 --- a/arch/arm/mach-vexpress/dcscb.c +++ b/arch/arm/mach-vexpress/dcscb.c @@ -133,32 +133,8 @@ static void dcscb_power_down(void) if (last_man && __mcpm_outbound_enter_critical(cpu, cluster)) { arch_spin_unlock(&dcscb_lock); - /* - * Flush all cache levels for this cluster. - * - * To do so we do: - * - Clear the SCTLR.C bit to prevent further cache allocations - * - Flush the whole cache - * - Clear the ACTLR "SMP" bit to disable local coherency - * - * Let's do it in the safest possible way i.e. with - * no memory access within the following sequence - * including to the stack. - */ - asm volatile( - "mrc p15, 0, r0, c1, c0, 0 @ get CR \n\t" - "bic r0, r0, #"__stringify(CR_C)" \n\t" - "mcr p15, 0, r0, c1, c0, 0 @ set CR \n\t" - "isb \n\t" - "bl v7_flush_dcache_all \n\t" - "clrex \n\t" - "mrc p15, 0, r0, c1, c0, 1 @ get AUXCR \n\t" - "bic r0, r0, #(1 << 6) @ disable local coherency \n\t" - "mcr p15, 0, r0, c1, c0, 1 @ set AUXCR \n\t" - "isb \n\t" - "dsb " - : : : "r0","r1","r2","r3","r4","r5","r6","r7", - "r9","r10","r11","lr","memory"); + /* Flush all cache levels for this cluster. */ + v7_disable_flush_cache(all); /* * This is a harmless no-op. On platforms with a real @@ -177,24 +153,8 @@ static void dcscb_power_down(void) } else { arch_spin_unlock(&dcscb_lock); - /* - * Flush the local CPU cache. - * Let's do it in the safest possible way as above. - */ - asm volatile( - "mrc p15, 0, r0, c1, c0, 0 @ get CR \n\t" - "bic r0, r0, #"__stringify(CR_C)" \n\t" - "mcr p15, 0, r0, c1, c0, 0 @ set CR \n\t" - "isb \n\t" - "bl v7_flush_dcache_louis \n\t" - "clrex \n\t" - "mrc p15, 0, r0, c1, c0, 1 @ get AUXCR \n\t" - "bic r0, r0, #(1 << 6) @ disable local coherency \n\t" - "mcr p15, 0, r0, c1, c0, 1 @ set AUXCR \n\t" - "isb \n\t" - "dsb " - : : : "r0","r1","r2","r3","r4","r5","r6","r7", - "r9","r10","r11","lr","memory"); + /* Flush the local CPU cache. */ + v7_disable_flush_cache(louis); } __mcpm_cpu_down(cpu, cluster); diff --git a/arch/arm/mach-vexpress/tc2_pm.c b/arch/arm/mach-vexpress/tc2_pm.c index dfb55d45b6..fd8bc2d931 100644 --- a/arch/arm/mach-vexpress/tc2_pm.c +++ b/arch/arm/mach-vexpress/tc2_pm.c @@ -134,26 +134,7 @@ static void tc2_pm_down(u64 residency) : : "r" (0x400) ); } - /* - * We need to disable and flush the whole (L1 and L2) cache. - * Let's do it in the safest possible way i.e. with - * no memory access within the following sequence - * including the stack. - */ - asm volatile( - "mrc p15, 0, r0, c1, c0, 0 @ get CR \n\t" - "bic r0, r0, #"__stringify(CR_C)" \n\t" - "mcr p15, 0, r0, c1, c0, 0 @ set CR \n\t" - "isb \n\t" - "bl v7_flush_dcache_all \n\t" - "clrex \n\t" - "mrc p15, 0, r0, c1, c0, 1 @ get AUXCR \n\t" - "bic r0, r0, #(1 << 6) @ disable local coherency \n\t" - "mcr p15, 0, r0, c1, c0, 1 @ set AUXCR \n\t" - "isb \n\t" - "dsb " - : : : "r0","r1","r2","r3","r4","r5","r6","r7", - "r9","r10","r11","lr","memory"); + v7_disable_flush_cache(all); cci_disable_port_by_cpu(mpidr); @@ -169,24 +150,7 @@ static void tc2_pm_down(u64 residency) arch_spin_unlock(&tc2_pm_lock); - /* - * We need to disable and flush only the L1 cache. - * Let's do it in the safest possible way as above. - */ - asm volatile( - "mrc p15, 0, r0, c1, c0, 0 @ get CR \n\t" - "bic r0, r0, #"__stringify(CR_C)" \n\t" - "mcr p15, 0, r0, c1, c0, 0 @ set CR \n\t" - "isb \n\t" - "bl v7_flush_dcache_louis \n\t" - "clrex \n\t" - "mrc p15, 0, r0, c1, c0, 1 @ get AUXCR \n\t" - "bic r0, r0, #(1 << 6) @ disable local coherency \n\t" - "mcr p15, 0, r0, c1, c0, 1 @ set AUXCR \n\t" - "isb \n\t" - "dsb " - : : : "r0","r1","r2","r3","r4","r5","r6","r7", - "r9","r10","r11","lr","memory"); + v7_disable_flush_cache(louis); } __mcpm_cpu_down(cpu, cluster);