| Message ID | b1cc86d5330df59e75914ab3c3a773900b589455.1542546735.git.mesihkilinc@gmail.com (mailing list archive) |
|---|---|
| State | Superseded, archived |
| Headers | show |
| Series | initial support for "suniv" Allwinner new ARM9 SoC | expand |
On Sun, Nov 18, 2018 at 05:17:12PM +0300, Mesih Kilinc wrote: > F1C100s is one product with the suniv die, which has a 32MiB co-packaged > DDR1 DRAM chip. As we have the support for suniv pin controller and CCU now, add a > initial DTSI for it. > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io> > Signed-off-by: Mesih Kilinc <mesihkilnc@gmail.com> > --- > arch/arm/boot/dts/suniv-f1c100s.dtsi | 158 +++++++++++++++++++++++++++++++++++ > 1 file changed, 158 insertions(+) > create mode 100644 arch/arm/boot/dts/suniv-f1c100s.dtsi > > diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi > new file mode 100644 > index 0000000..d98f658 > --- /dev/null > +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi > @@ -0,0 +1,158 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR X11) > +/* > + * Copyright 2018 Icenowy Zheng <icenowy@aosc.io> > + * Copyright 2018 Mesih Kilinc <mesihkilinc@gmail.com> > + */ > + > +#include <dt-bindings/clock/suniv-ccu-f1c100s.h> > +#include <dt-bindings/reset/suniv-ccu-f1c100s.h> > + > +/ { > + #address-cells = <1>; > + #size-cells = <1>; > + interrupt-parent = <&intc>; > + > + clocks { > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + osc24M: clk-24M { > + #clock-cells = <0>; > + compatible = "fixed-clock"; > + clock-frequency = <24000000>; > + clock-output-names = "osc24M"; > + }; > + > + osc32k: clk-32k { > + #clock-cells = <0>; > + compatible = "fixed-clock"; > + clock-frequency = <32768>; > + clock-output-names = "osc32k"; > + }; > + > + fake100M: clk-100M { > + #clock-cells = <0>; > + compatible = "fixed-clock"; > + clock-frequency = <100000000>; > + clock-output-names = "fake-100M"; > + }; Why do you need that fake clock? > + }; > + > + cpus { > + #address-cells = <0>; > + #size-cells = <0>; > + > + cpu { > + compatible = "arm,arm926ej-s"; > + device_type = "cpu"; > + }; > + }; > + > + soc { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + sram-controller@1c00000 { > + compatible = "allwinner,sun4i-a10-sram-controller"; You should have a compatible for that SoC there (possibly keeping the A10 compatible if that makes sense). > + reg = <0x01c00000 0x30>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + sram_d: sram@10000 { > + compatible = "mmio-sram"; > + reg = <0x00010000 0x1000>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0 0x00010000 0x1000>; > + > + otg_sram: sram-section@0 { > + compatible = "allwinner,sun4i-a10-sram-d"; Ditto > + reg = <0x0000 0x1000>; > + status = "disabled"; > + }; > + }; > + }; > + > + ccu: clock@1c20000 { > + compatible = "allwinner,suniv-f1c100s-ccu"; > + reg = <0x01c20000 0x400>; > + clocks = <&osc24M>, <&osc32k>; > + clock-names = "hosc", "losc"; > + #clock-cells = <1>; > + #reset-cells = <1>; > + }; > + > + intc: interrupt-controller@1c20400 { > + compatible = "allwinner,suniv-f1c100s-ic"; > + reg = <0x01c20400 0x400>; > + interrupt-controller; > + #interrupt-cells = <1>; > + }; > + > + pio: pinctrl@1c20800 { > + compatible = "allwinner,suniv-f1c100s-pinctrl"; > + reg = <0x01c20800 0x400>; > + interrupts = <38>, <39>, <40>; > + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>; > + clock-names = "apb", "hosc", "losc"; > + gpio-controller; > + interrupt-controller; > + #interrupt-cells = <3>; > + #gpio-cells = <3>; > + > + uart0_pins_a: uart-pins-pe { > + pins = "PE0", "PE1"; > + function = "uart0"; > + }; > + }; > + > + timer@1c20c00 { > + compatible = "allwinner,suniv-f1c100s-timer"; > + reg = <0x01c20c00 0x90>; > + interrupts = <13>; > + clocks = <&osc24M>; > + }; > + > + wdt: watchdog@1c20ca0 { > + compatible = "allwinner,sun6i-a31-wdt"; Ditto. Thanks! Maxime
diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi new file mode 100644 index 0000000..d98f658 --- /dev/null +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi @@ -0,0 +1,158 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR X11) +/* + * Copyright 2018 Icenowy Zheng <icenowy@aosc.io> + * Copyright 2018 Mesih Kilinc <mesihkilinc@gmail.com> + */ + +#include <dt-bindings/clock/suniv-ccu-f1c100s.h> +#include <dt-bindings/reset/suniv-ccu-f1c100s.h> + +/ { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + osc24M: clk-24M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "osc24M"; + }; + + osc32k: clk-32k { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "osc32k"; + }; + + fake100M: clk-100M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + clock-output-names = "fake-100M"; + }; + }; + + cpus { + #address-cells = <0>; + #size-cells = <0>; + + cpu { + compatible = "arm,arm926ej-s"; + device_type = "cpu"; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sram-controller@1c00000 { + compatible = "allwinner,sun4i-a10-sram-controller"; + reg = <0x01c00000 0x30>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sram_d: sram@10000 { + compatible = "mmio-sram"; + reg = <0x00010000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00010000 0x1000>; + + otg_sram: sram-section@0 { + compatible = "allwinner,sun4i-a10-sram-d"; + reg = <0x0000 0x1000>; + status = "disabled"; + }; + }; + }; + + ccu: clock@1c20000 { + compatible = "allwinner,suniv-f1c100s-ccu"; + reg = <0x01c20000 0x400>; + clocks = <&osc24M>, <&osc32k>; + clock-names = "hosc", "losc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + intc: interrupt-controller@1c20400 { + compatible = "allwinner,suniv-f1c100s-ic"; + reg = <0x01c20400 0x400>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + pio: pinctrl@1c20800 { + compatible = "allwinner,suniv-f1c100s-pinctrl"; + reg = <0x01c20800 0x400>; + interrupts = <38>, <39>, <40>; + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + interrupt-controller; + #interrupt-cells = <3>; + #gpio-cells = <3>; + + uart0_pins_a: uart-pins-pe { + pins = "PE0", "PE1"; + function = "uart0"; + }; + }; + + timer@1c20c00 { + compatible = "allwinner,suniv-f1c100s-timer"; + reg = <0x01c20c00 0x90>; + interrupts = <13>; + clocks = <&osc24M>; + }; + + wdt: watchdog@1c20ca0 { + compatible = "allwinner,sun6i-a31-wdt"; + reg = <0x01c20ca0 0x20>; + }; + + uart0: serial@1c25000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c25000 0x400>; + interrupts = <1>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART0>; + resets = <&ccu RST_BUS_UART0>; + status = "disabled"; + }; + + uart1: serial@1c25400 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c25400 0x400>; + interrupts = <2>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART1>; + resets = <&ccu RST_BUS_UART1>; + status = "disabled"; + }; + + uart2: serial@1c25800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c25800 0x400>; + interrupts = <3>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART2>; + resets = <&ccu RST_BUS_UART2>; + status = "disabled"; + }; + }; +};