[PATCH/RFC,5/6] arm64: dts: renesas: Add support for H3ULCB with R-Car H3Ne-1.7G

Commit Message

Geert Uytterhoeven July 20, 2022, 8:08 a.m. UTC

Add support for the Renesas R-Car Starter Kit Premier equipped with an
R-Car H3Ne-1.7G SiP.

Signed-off-by: Geert Uytterhoeven <[e-mail]>
---
 arch/arm64/boot/dts/renesas/Makefile          |  1 +
 arch/arm64/boot/dts/renesas/r8a779mb-ulcb.dts | 53 +++++++++++++++++++
 2 files changed, 54 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/r8a779mb-ulcb.dts

Patch

diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index b83a5fcad1f3a4ba..68f64649f9fc362d 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -78,6 +78,7 @@  dtb-$(CONFIG_ARCH_R8A77961) += r8a779m3-ulcb-kf.dtb
 dtb-$(CONFIG_ARCH_R8A77965) += r8a779m5-salvator-xs.dtb
 
 dtb-$(CONFIG_ARCH_R8A77951) += r8a779mb-salvator-xs.dtb
+dtb-$(CONFIG_ARCH_R8A77951) += r8a779mb-ulcb.dtb
 
 dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043u11-smarc.dtb
 
diff --git a/arch/arm64/boot/dts/renesas/r8a779mb-ulcb.dts b/arch/arm64/boot/dts/renesas/r8a779mb-ulcb.dts
new file mode 100644
index 0000000000000000..f17aa4b824abe6a6
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a779mb-ulcb.dts
@@ -0,0 +1,53 @@ 
+// SPDX-License-Identifier: (GPL-2.0 or MIT)
+/*
+ * Device Tree Source for the H3ULCB (R-Car Starter Kit Premier) with R-Car
+ * H3Ne-1.7G
+ *
+ * Copyright (C) 2022 Glider bv
+ *
+ * Based on r8a77951-ulcb.dts
+ * Copyright (C) 2016 Cogent Embedded, Inc.
+ */
+
+/dts-v1/;
+#include "r8a779mb.dtsi"
+#include "ulcb.dtsi"
+
+/ {
+	model = "Renesas H3ULCB board based on r8a779mb";
+	compatible = "renesas,h3ulcb", "renesas,r8a779mb", "renesas,r8a7795";
+
+	memory@48000000 {
+		device_type = "memory";
+		/* first 128MB is reserved for secure area. */
+		reg = <0x0 0x48000000 0x0 0x38000000>;
+	};
+
+	memory@500000000 {
+		device_type = "memory";
+		reg = <0x5 0x00000000 0x0 0x40000000>;
+	};
+
+	memory@600000000 {
+		device_type = "memory";
+		reg = <0x6 0x00000000 0x0 0x40000000>;
+	};
+
+	memory@700000000 {
+		device_type = "memory";
+		reg = <0x7 0x00000000 0x0 0x40000000>;
+	};
+};
+
+&du {
+	clocks = <&cpg CPG_MOD 724>,
+		 <&cpg CPG_MOD 723>,
+		 <&cpg CPG_MOD 722>,
+		 <&cpg CPG_MOD 721>,
+		 <&versaclock5 1>,
+		 <&versaclock5 3>,
+		 <&versaclock5 4>,
+		 <&versaclock5 2>;
+	clock-names = "du.0", "du.1", "du.2", "du.3",
+		      "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
+};