From patchwork Mon Feb 9 06:18:36 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Anand X-Patchwork-Id: 5798391 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id F26639F30C for ; Mon, 9 Feb 2015 06:21:12 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 26D512011B for ; Mon, 9 Feb 2015 06:21:12 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 49BB120103 for ; Mon, 9 Feb 2015 06:21:11 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YKhgg-000302-Ao; Mon, 09 Feb 2015 06:19:14 +0000 Received: from mx1.redhat.com ([209.132.183.28]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1YKhgd-0002yk-R2 for linux-arm-kernel@lists.infradead.org; Mon, 09 Feb 2015 06:19:12 +0000 Received: from int-mx14.intmail.prod.int.phx2.redhat.com (int-mx14.intmail.prod.int.phx2.redhat.com [10.5.11.27]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id t196IgTk009263 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 9 Feb 2015 01:18:42 -0500 Received: from localhost (vpn-63-174.rdu2.redhat.com [10.10.63.174]) by int-mx14.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id t196IdV7004298 (version=TLSv1/SSLv3 cipher=AES128-GCM-SHA256 bits=128 verify=NO); Mon, 9 Feb 2015 01:18:41 -0500 From: Pratyush Anand To: linux-arm-kernel@lists.infradead.org, linux@arm.linux.org.uk Subject: [PATCH] ARM64: gic: Do not allow bypass FIQ signals to reach to processor Date: Mon, 9 Feb 2015 11:48:36 +0530 Message-Id: X-Scanned-By: MIMEDefang 2.68 on 10.5.11.27 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150208_221911_940651_C5D904D1 X-CRM114-Status: UNSURE ( 9.97 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -5.0 (-----) Cc: Pratyush Anand X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP In some case few signals of an IP(like PMU Overflow in APM88xx0x) can be mapped to nLEGACYFIQ, ie nFIQ of CPU. Until ARM64 supports FIQ handling, we will get nice "Bad mode in FIQ handler detected" Therefore force FIQBypDisGrp1 to '1', so that bypass FIQ signal is not signaled to the processor. Signed-off-by: Pratyush Anand --- drivers/irqchip/irq-gic.c | 9 ++++++++- include/linux/irqchip/arm-gic.h | 1 + 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index d617ee5a3d8a..525dfc966e60 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -362,7 +362,14 @@ static void gic_cpu_if_up(void) */ bypass = readl(cpu_base + GIC_CPU_CTRL); bypass &= GICC_DIS_BYPASS_MASK; - +#ifdef CONFIG_ARM64 + /* FIXME: when ARM64 starts supporting FIQ mode. + * + * Until ARM64 supports FIQ handling, force FIQBypDisGrp1 to + * '1', so that bypass FIQ signal is not signaled to the processor. + */ + bypass |= GICC_DIS_BYPASS_FIQ_TO_CPU; +#endif writel_relaxed(bypass | GICC_ENABLE, cpu_base + GIC_CPU_CTRL); } diff --git a/include/linux/irqchip/arm-gic.h b/include/linux/irqchip/arm-gic.h index 71d706d5f169..c9fdd1972625 100644 --- a/include/linux/irqchip/arm-gic.h +++ b/include/linux/irqchip/arm-gic.h @@ -25,6 +25,7 @@ #define GICC_INT_PRI_THRESHOLD 0xf0 #define GICC_IAR_INT_ID_MASK 0x3ff #define GICC_INT_SPURIOUS 1023 +#define GICC_DIS_BYPASS_FIQ_TO_CPU (1 << 5) #define GICC_DIS_BYPASS_MASK 0x1e0 #define GIC_DIST_CTRL 0x000