From patchwork Fri Jan 8 16:02:16 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cyrille Pitchen X-Patchwork-Id: 7987501 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 1A54E9F1CC for ; Fri, 8 Jan 2016 16:06:16 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2BD8A2014A for ; Fri, 8 Jan 2016 16:06:15 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3C1A5200E9 for ; Fri, 8 Jan 2016 16:06:14 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aHZWl-0000Ug-1V; Fri, 08 Jan 2016 16:04:35 +0000 Received: from eusmtp01.atmel.com ([212.144.249.243]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1aHZW4-000850-1v; Fri, 08 Jan 2016 16:04:07 +0000 Received: from tenerife.corp.atmel.com (10.161.101.13) by eusmtp01.atmel.com (10.161.101.31) with Microsoft SMTP Server id 14.3.235.1; Fri, 8 Jan 2016 17:03:22 +0100 From: Cyrille Pitchen To: , Subject: [PATCH linux-next v2 04/14] mtd: spi-nor: fix support of Macronix memories Date: Fri, 8 Jan 2016 17:02:16 +0100 Message-ID: X-Mailer: git-send-email 1.8.2.2 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160108_080352_985115_52543B08 X-CRM114-Status: GOOD ( 18.23 ) X-Spam-Score: -4.2 (----) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, boris.brezillon@free-electrons.com, vigneshr@ti.com, pawel.moll@arm.com, devicetree@vger.kernel.org, ijc+devicetree@hellion.org.uk, nicolas.ferre@atmel.com, linux-kernel@vger.kernel.org, robh+dt@kernel.org, galak@codeaurora.org, mark.rutland@arm.com, Cyrille Pitchen , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch fixes the support of Macronix memories. Especially we avoid updating the Status Register when not needed as the Quad Enable (QE) bit is a non-volatile bit. Also we add comments to explain why we use some Fast Read op codes rather than others. Signed-off-by: Cyrille Pitchen --- drivers/mtd/spi-nor/spi-nor.c | 81 ++++++++++++++++++++++++++++++++++++++----- 1 file changed, 72 insertions(+), 9 deletions(-) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index 8793cebbe5a9..042ac49d6188 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -1115,6 +1115,11 @@ static int macronix_quad_enable(struct spi_nor *nor) val = read_sr(nor); if (val < 0) return val; + + if (likely(val & SR_QUAD_EN_MX)) + return 0; + dev_warn(nor->dev, "Macronix Quad mode disabled, enable it\n"); + write_enable(nor); write_sr(nor, val | SR_QUAD_EN_MX); @@ -1169,21 +1174,73 @@ static int spansion_quad_enable(struct spi_nor *nor) return 0; } +static int macronix_set_quad_mode(struct spi_nor *nor) +{ + int status; + + /* Check whether the QPI mode is enabled. */ + if (nor->read_proto == SNOR_PROTO_4_4_4) { + /* + * Since the QPI mode is enabled, the Quad Enabled (QE) + * non-volatile bit is already set. + * However in QPI mode, only the Fast Read 1-4-4 (0xeb) + * op code is supported. + * WARNING: we should take care about the performance + * enhance toggling bits P0-P7 written during the + * dummy/mode cycles to avoid entering the continuous + * read (performance enhance) mode by mistake! + */ + nor->read_opcode = SPINOR_OP_READ_1_4_4; + return 0; + } + + /* + * The QPI mode is disabled but we still need to set the QE bit: + * this disables the reset and write protect features and + * frees the associated pins so they can be used as the 3rd + * and 4th I/O lines required by Quad SPI commands. + * Also we'd rather use the Fast Read 1-1-4 (0x6b) op code than + * the Fast Read 1-4-4 (0xeb) op code so we don't care about + * entering the continuous read mode by mistake if some + * performance enhance toggling bits P0-P7 were written during + * dummy/mode cycles. + */ + status = macronix_quad_enable(nor); + if (status) { + dev_err(nor->dev, "Macronix quad-read not enabled\n"); + return status; + } + nor->read_proto = SNOR_PROTO_1_1_4; + nor->read_opcode = SPINOR_OP_READ_1_1_4; + return 0; +} + +/* + * For both Macronix Dual and Single modes, we don't care about the value of + * the Quad Enabled (QE) bit since the memory still replies to Dual or Single + * SPI commands. + */ + +static int macronix_set_dual_mode(struct spi_nor *nor) +{ + nor->read_proto = SNOR_PROTO_1_1_2; + nor->read_opcode = SPINOR_OP_READ_1_1_2; + return 0; +} + +static int macronix_set_single_mode(struct spi_nor *nor) +{ + nor->read_proto = SNOR_PROTO_1_1_1; + return 0; +} + static int set_quad_mode(struct spi_nor *nor, const struct flash_info *info) { int status; switch (JEDEC_MFR(info)) { case SNOR_MFR_MACRONIX: - status = macronix_quad_enable(nor); - if (status) { - dev_err(nor->dev, "Macronix quad-read not enabled\n"); - return -EINVAL; - } - /* Check whether Macronix QPI mode is enabled. */ - if (nor->read_proto != SNOR_PROTO_4_4_4) - nor->read_proto = SNOR_PROTO_1_1_4; - break; + return macronix_set_quad_mode(nor); case SNOR_MFR_MICRON: /* Check whether Micron Quad mode is enabled. */ @@ -1211,6 +1268,9 @@ static int set_quad_mode(struct spi_nor *nor, const struct flash_info *info) static int set_dual_mode(struct spi_nor *nor, const struct flash_info *info) { switch (JEDEC_MFR(info)) { + case SNOR_MFR_MACRONIX: + return macronix_set_dual_mode(nor); + case SNOR_MFR_MICRON: /* Check whether Micron Dual mode is enabled. */ if (nor->read_proto != SNOR_PROTO_2_2_2) @@ -1229,6 +1289,9 @@ static int set_dual_mode(struct spi_nor *nor, const struct flash_info *info) static int set_single_mode(struct spi_nor *nor, const struct flash_info *info) { switch (JEDEC_MFR(info)) { + case SNOR_MFR_MACRONIX: + return macronix_set_single_mode(nor); + default: nor->read_proto = SNOR_PROTO_1_1_1; break;