From patchwork Thu Nov 8 18:04:26 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Josh Cartwright X-Patchwork-Id: 1717441 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id C7CF03FCDF for ; Thu, 8 Nov 2012 19:56:59 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TWYBU-0004To-94; Thu, 08 Nov 2012 19:54:40 +0000 Received: from mailserver6.natinst.com ([130.164.80.6] helo=spamkiller06.natinst.com) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TWYB0-0004Oz-W9 for linux-arm-kernel@lists.infradead.org; Thu, 08 Nov 2012 19:54:13 +0000 Received: from mailserv58-us.natinst.com (nb-hsrp-1338.natinst.com [130.164.19.133]) by spamkiller06.natinst.com (8.14.5/8.14.5) with ESMTP id qA8Js7op005853; Thu, 8 Nov 2012 13:54:07 -0600 Received: from beefymiracle.amer.corp.natinst.com ([130.164.14.197]) by mailserv58-us.natinst.com (Lotus Domino Release 8.5.3FP2 HF169) with ESMTP id 2012110813540703-1128201 ; Thu, 8 Nov 2012 13:54:07 -0600 Received: by beefymiracle.amer.corp.natinst.com (Postfix, from userid 1000) id 2EB3D613C9; Thu, 8 Nov 2012 13:54:17 -0600 (CST) Message-Id: In-Reply-To: References: From: Josh Cartwright Date: Thu, 8 Nov 2012 12:04:26 -0600 Subject: [PATCH v2 3/5] ARM: zynq: use zynq clk bindings To: Michal Simek , John Linn , arm@kernel.org X-MIMETrack: Itemize by SMTP Server on MailServ58-US/AUS/H/NIC(Release 8.5.3FP2 HF169|September 14, 2012) at 11/08/2012 01:54:07 PM, Serialize by Router on MailServ58-US/AUS/H/NIC(Release 8.5.3FP2 HF169|September 14, 2012) at 11/08/2012 01:54:07 PM, Serialize complete at 11/08/2012 01:54:07 PM X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:5.9.8185, 1.0.431, 0.0.0000 definitions=2012-11-08_04:2012-11-08, 2012-11-08, 1970-01-01 signatures=0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20121108_145411_255140_1F9604A6 X-CRM114-Status: GOOD ( 14.50 ) X-Spam-Score: -1.9 (-) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-1.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Make the Zynq platform use the newly created zynq clk bindings. Signed-off-by: Josh Cartwright --- arch/arm/Kconfig | 1 + arch/arm/boot/dts/zynq-7000.dtsi | 56 ++++++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/zynq-zc702.dts | 4 +++ arch/arm/mach-zynq/common.c | 11 ++++++++ drivers/clk/Makefile | 1 + 5 files changed, 73 insertions(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 21ed87b..ccfe0ab 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -959,6 +959,7 @@ config ARCH_ZYNQ bool "Xilinx Zynq ARM Cortex A9 Platform" select ARM_AMBA select ARM_GIC + select COMMON_CLK select CPU_V7 select GENERIC_CLOCKEVENTS select ICST diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi index 8b30e59..bb3085c 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++ b/arch/arm/boot/dts/zynq-7000.dtsi @@ -53,5 +53,61 @@ interrupts = <0 50 4>; clock = <50000000>; }; + + slcr: slcr@f8000000 { + compatible = "xlnx,zynq-slcr"; + reg = <0xF8000000 0x1000>; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + ps_clk: ps_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + /* clock-frequency set in board-specific file */ + clock-output-names = "ps_clk"; + }; + armpll: armpll { + #clock-cells = <0>; + compatible = "xlnx,zynq-pll"; + clocks = <&ps_clk>; + reg = <0x100 0x110>; + clock-output-names = "armpll"; + }; + ddrpll: ddrpll { + #clock-cells = <0>; + compatible = "xlnx,zynq-pll"; + clocks = <&ps_clk>; + reg = <0x104 0x114>; + clock-output-names = "ddrpll"; + }; + iopll: iopll { + #clock-cells = <0>; + compatible = "xlnx,zynq-pll"; + clocks = <&ps_clk>; + reg = <0x108 0x118>; + clock-output-names = "iopll"; + }; + uart_clk: uart_clk { + #clock-cells = <1>; + compatible = "xlnx,zynq-periph-clock"; + clocks = <&iopll &armpll &ddrpll>; + reg = <0x154>; + clock-output-names = "uart0_ref_clk", + "uart1_ref_clk"; + }; + cpu_clk: cpu_clk { + #clock-cells = <1>; + compatible = "xlnx,zynq-cpu-clock"; + clocks = <&iopll &armpll &ddrpll>; + reg = <0x120 0x1C4>; + clock-output-names = "cpu_6x4x", + "cpu_3x2x", + "cpu_2x", + "cpu_1x"; + }; + }; + }; }; }; diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts index e25a307..86f44d5 100644 --- a/arch/arm/boot/dts/zynq-zc702.dts +++ b/arch/arm/boot/dts/zynq-zc702.dts @@ -28,3 +28,7 @@ }; }; + +&ps_clk { + clock-frequency = <33333330>; +}; diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c index 5441323..79bf5fb 100644 --- a/arch/arm/mach-zynq/common.c +++ b/arch/arm/mach-zynq/common.c @@ -19,6 +19,8 @@ #include #include #include +#include +#include #include #include #include @@ -96,6 +98,15 @@ static struct map_desc io_desc[] __initdata = { static void __init xilinx_zynq_timer_init(void) { + struct device_node *np; + void __iomem *slcr; + + np = of_find_compatible_node(NULL, NULL, "xlnx,zynq-slcr"); + slcr = of_iomap(np, 0); + WARN_ON(!slcr); + + xilinx_zynq_clocks_init(slcr); + xttcpss_timer_init(); } diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 71a25b9..d35a34c 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -19,6 +19,7 @@ endif obj-$(CONFIG_MACH_LOONGSON1) += clk-ls1x.o obj-$(CONFIG_ARCH_U8500) += ux500/ obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o +obj-$(CONFIG_ARCH_ZYNQ) += clk-zynq.o # Chip specific obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o