| Message ID | bc000ac53bb1b3ae1a951bbcf372caf6336d2a19.1345524670.git.afzal@ti.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
* Afzal Mohammed <afzal@ti.com> [120821 03:46]: > Generic gpmc timing calculation helper is available now, use > it instead of custom timing calculation. This hangs n800 during the boot. Tony
Hi Tony,
On Sat, Aug 25, 2012 at 01:16:30, Tony Lindgren wrote:
> This hangs n800 during the boot.
Shall I read the above as n800 boot without patch 10/10,
but with the other patches in this series ?
As per the board file, n800 has tusb6010 as well as
OneNAND in sync read & async write mode, was OneNAND
working without 10/10.
Do you have any idea, which timing could have gone wrong,
can you please sent me DEBUG enabled gpmc log with and
without 10/10.
Regards
Afzal
Hi Tony, On Mon, Aug 27, 2012 at 14:04:44, Mohammed, Afzal wrote: > On Sat, Aug 25, 2012 at 01:16:30, Tony Lindgren wrote: > > This hangs n800 during the boot. > > Shall I read the above as n800 boot without patch 10/10, > but with the other patches in this series ? > > As per the board file, n800 has tusb6010 as well as > OneNAND in sync read & async write mode, was OneNAND > working without 10/10. > > Do you have any idea, which timing could have gone wrong, > can you please sent me DEBUG enabled gpmc log with and > without 10/10. Can you please sent me GPMC DEBUG enabled logs with and without this series. Regards Afzal
Hi Tony, On Mon, Sep 03, 2012 at 11:04:10, Mohammed, Afzal wrote: > On Mon, Aug 27, 2012 at 14:04:44, Mohammed, Afzal wrote: > > On Sat, Aug 25, 2012 at 01:16:30, Tony Lindgren wrote: > > > This hangs n800 during the boot. Paul reported that n800 stopped booting on OMAP baseline [1] due to an mmc issue and has posted a solution [2]. Are you facing the same issue ?, if so, then it is not due to this series. I tried to get an n800, but has been unsuccessful. Regards Afzal [1] http://marc.info/?l=linux-omap&m=134685988517580&w=2 [2] http://www.spinics.net/lists/arm-kernel/msg190879.html > > > > Shall I read the above as n800 boot without patch 10/10, > > but with the other patches in this series ? > > > > As per the board file, n800 has tusb6010 as well as > > OneNAND in sync read & async write mode, was OneNAND > > working without 10/10. > > > > Do you have any idea, which timing could have gone wrong, > > can you please sent me DEBUG enabled gpmc log with and > > without 10/10. > > Can you please sent me GPMC DEBUG enabled logs with and > without this series.
* Mohammed, Afzal <afzal@ti.com> [120906 00:40]: > Hi Tony, > > On Mon, Sep 03, 2012 at 11:04:10, Mohammed, Afzal wrote: > > On Mon, Aug 27, 2012 at 14:04:44, Mohammed, Afzal wrote: > > > On Sat, Aug 25, 2012 at 01:16:30, Tony Lindgren wrote: > > > > > This hangs n800 during the boot. > > Paul reported that n800 stopped booting on OMAP baseline [1] > due to an mmc issue and has posted a solution [2]. > > Are you facing the same issue ?, if so, then it is not > due to this series. No that's a separate issue. Your series works except for this patch makes thing hang. Regards, Tony > I tried to get an n800, but has been unsuccessful. > > Regards > Afzal > > [1] http://marc.info/?l=linux-omap&m=134685988517580&w=2 > [2] http://www.spinics.net/lists/arm-kernel/msg190879.html > > > > > > > > Shall I read the above as n800 boot without patch 10/10, > > > but with the other patches in this series ? > > > > > > As per the board file, n800 has tusb6010 as well as > > > OneNAND in sync read & async write mode, was OneNAND > > > working without 10/10. > > > > > > Do you have any idea, which timing could have gone wrong, > > > can you please sent me DEBUG enabled gpmc log with and > > > without 10/10. > > > > Can you please sent me GPMC DEBUG enabled logs with and > > without this series. >
+ Rajendra
Hi
On Thu, 6 Sep 2012, Mohammed, Afzal wrote:
> I tried to get an n800, but has been unsuccessful.
We took an n800 to TII a few years ago, hopefully you can find it. Cc'ing
Rajendra who might know where it is.
- Paul
* Tony Lindgren <tony@atomide.com> [120906 13:45]: > * Mohammed, Afzal <afzal@ti.com> [120906 00:40]: > > Hi Tony, > > > > On Mon, Sep 03, 2012 at 11:04:10, Mohammed, Afzal wrote: > > > On Mon, Aug 27, 2012 at 14:04:44, Mohammed, Afzal wrote: > > > > On Sat, Aug 25, 2012 at 01:16:30, Tony Lindgren wrote: > > > > > > > This hangs n800 during the boot. > > > > Paul reported that n800 stopped booting on OMAP baseline [1] > > due to an mmc issue and has posted a solution [2]. > > > > Are you facing the same issue ?, if so, then it is not > > due to this series. > > No that's a separate issue. Your series works except for > this patch makes thing hang. Here are the timing changes with and without this patch from my n800. You can just diff the two files to see some differences. Regards, Tony GPMC CS1: cs_on : 1 ticks, 9 ns (was 0 ticks) 9 ns GPMC CS1: cs_rd_off : 8 ticks, 72 ns (was 5 ticks) 72 ns GPMC CS1: cs_wr_off : 8 ticks, 72 ns (was 5 ticks) 72 ns GPMC CS1: adv_on : 6 ticks, 54 ns (was 0 ticks) 54 ns GPMC CS1: adv_rd_off: 7 ticks, 63 ns (was 3 ticks) 63 ns GPMC CS1: adv_wr_off: 7 ticks, 63 ns (was 3 ticks) 63 ns GPMC CS1: oe_on : 7 ticks, 63 ns (was 4 ticks) 63 ns GPMC CS1: oe_off : 8 ticks, 72 ns (was 5 ticks) 72 ns GPMC CS1: we_on : 8 ticks, 72 ns (was 4 ticks) 72 ns GPMC CS1: we_off : 8 ticks, 72 ns (was 5 ticks) 72 ns GPMC CS1: rd_cycle : 9 ticks, 82 ns (was 5 ticks) 82 ns GPMC CS1: wr_cycle : 9 ticks, 82 ns (was 5 ticks) 82 ns GPMC CS1: access : 7 ticks, 63 ns (was 5 ticks) 63 ns GPMC CS1: page_burst_access: 0 ticks, 0 ns (was 0 ticks) 0 ns GPMC CS1: bus_turnaround: 0 ticks, 0 ns (was 0 ticks) 0 ns GPMC CS1: cycle2cycle_delay: 0 ticks, 0 ns (was 0 ticks) 0 ns GPMC CS1: wait_monitoring: 0 ticks, 0 ns (was 0 ticks) 0 ns GPMC CS1: clk_activation: 0 ticks, 0 ns (was 0 ticks) 0 ns GPMC CS4: cs_on : 1 ticks, 9 ns (was 0 ticks) 9 ns GPMC CS4: cs_rd_off : 16 ticks, 145 ns (was 7 ticks) 145 ns GPMC CS4: cs_wr_off : 16 ticks, 145 ns (was 7 ticks) 145 ns GPMC CS4: adv_on : 6 ticks, 54 ns (was 2 ticks) 54 ns GPMC CS4: adv_rd_off: 7 ticks, 63 ns (was 4 ticks) 63 ns GPMC CS4: adv_wr_off: 7 ticks, 63 ns (was 4 ticks) 63 ns GPMC CS4: oe_on : 10 ticks, 91 ns (was 5 ticks) 91 ns GPMC CS4: oe_off : 16 ticks, 145 ns (was 7 ticks) 145 ns GPMC CS4: we_on : 10 ticks, 91 ns (was 5 ticks) 91 ns GPMC CS4: we_off : 16 ticks, 145 ns (was 6 ticks) 145 ns GPMC CS4: rd_cycle : 17 ticks, 154 ns (was 8 ticks) 154 ns GPMC CS4: wr_cycle : 17 ticks, 154 ns (was 8 ticks) 154 ns GPMC CS4: access : 15 ticks, 136 ns (was 6 ticks) 136 ns GPMC CS4: page_burst_access: 2 ticks, 18 ns (was 2 ticks) 18 ns GPMC CS4: bus_turnaround: 0 ticks, 0 ns (was 0 ticks) 0 ns GPMC CS4: cycle2cycle_delay: 0 ticks, 0 ns (was 0 ticks) 0 ns GPMC CS4: wait_monitoring: 0 ticks, 0 ns (was 0 ticks) 0 ns GPMC CS4: clk_activation: 1 ticks, 9 ns (was 0 ticks) 9 ns GPMC CS4 CLK period is 18 ns (div 2) TUSB 6010 ... OneNAND driver initializing GPMC CS0: cs_on : 0 ticks, 0 ns (was 0 ticks) 0 ns GPMC CS0: cs_rd_off : 10 ticks, 91 ns (was 12 ticks) 91 ns GPMC CS0: cs_wr_off : 12 ticks, 109 ns (was 9 ticks) 109 ns GPMC CS0: adv_on : 0 ticks, 0 ns (was 0 ticks) 0 ns GPMC CS0: adv_rd_off: 2 ticks, 18 ns (was 2 ticks) 18 ns GPMC CS0: adv_wr_off: 2 ticks, 18 ns (was 2 ticks) 18 ns GPMC CS0: oe_on : 3 ticks, 27 ns (was 2 ticks) 27 ns GPMC CS0: oe_off : 10 ticks, 91 ns (was 12 ticks) 91 ns GPMC CS0: we_on : 3 ticks, 27 ns (was 3 ticks) 27 ns GPMC CS0: we_off : 8 ticks, 72 ns (was 8 ticks) 72 ns GPMC CS0: rd_cycle : 13 ticks, 118 ns (was 13 ticks) 118 ns GPMC CS0: wr_cycle : 15 ticks, 136 ns (was 10 ticks) 136 ns GPMC CS0: access : 9 ticks, 82 ns (was 11 ticks) 82 ns GPMC CS0: page_burst_access: 0 ticks, 0 ns (was 2 ticks) 0 ns GPMC CS0: bus_turnaround: 0 ticks, 0 ns (was 0 ticks) 0 ns GPMC CS0: cycle2cycle_delay: 0 ticks, 0 ns (was 0 ticks) 0 ns GPMC CS0: wait_monitoring: 0 ticks, 0 ns (was 0 ticks) 0 ns GPMC CS0: clk_activation: 0 ticks, 0 ns (was 0 ticks) 0 ns GPMC CS0: cs_on : 0 ticks, 0 ns (was 0 ticks) 0 ns GPMC CS0: cs_rd_off : 14 ticks, 127 ns (was 10 ticks) 127 ns GPMC CS0: cs_wr_off : 12 ticks, 109 ns (was 12 ticks) 109 ns GPMC CS0: adv_on : 0 ticks, 0 ns (was 0 ticks) 0 ns GPMC CS0: adv_rd_off: 2 ticks, 18 ns (was 2 ticks) 18 ns GPMC CS0: adv_wr_off: 2 ticks, 18 ns (was 2 ticks) 18 ns GPMC CS0: oe_on : 3 ticks, 27 ns (was 3 ticks) 27 ns GPMC CS0: oe_off : 14 ticks, 127 ns (was 10 ticks) 127 ns GPMC CS0: we_on : 3 ticks, 27 ns (was 3 ticks) 27 ns GPMC CS0: we_off : 8 ticks, 72 ns (was 8 ticks) 72 ns GPMC CS0: rd_cycle : 16 ticks, 145 ns (was 13 ticks) 145 ns GPMC CS0: wr_cycle : 15 ticks, 136 ns (was 15 ticks) 136 ns GPMC CS0: access : 13 ticks, 118 ns (was 9 ticks) 118 ns GPMC CS0: page_burst_access: 3 ticks, 27 ns (was 0 ticks) 27 ns GPMC CS0: bus_turnaround: 0 ticks, 0 ns (was 0 ticks) 0 ns GPMC CS0: cycle2cycle_delay: 0 ticks, 0 ns (was 0 ticks) 0 ns GPMC CS0: wait_monitoring: 0 ticks, 0 ns (was 0 ticks) 0 ns GPMC CS0: clk_activation: 1 ticks, 9 ns (was 0 ticks) 9 ns GPMC CS0 CLK period is 27 ns (div 3) omap2-onenand omap2-onenand: initializing on CS0, phys base 0x04000000, virtual base c88c0000, freq 54 MHz OneNAND Manufacturer: Samsung (0xec) Muxed OneNAND(DDP) 256MB 1.8V 16-bit (0x48) OneNAND version = 0x0011 Chip support all block unlock onenand_wait: controller error! state 15 ctrl 0x0400 intr 0x8000 Scanning device for bad blocks Creating 5 MTD partitions on "omap2-onenand": 0x000000000000-0x000000020000 : "bootloader" 0x000000020000-0x000000080000 : "config" 0x000000080000-0x000000280000 : "kernel" 0x000000280000-0x000000680000 : "initfs" 0x000000680000-0x000010000000 : "rootfs" omap-dma-engine omap-dma-engine: allocating channel for 44 omap-dma-engine omap-dma-engine: allocating channel for 43 GPMC CS1: cs_on : 1 ticks, 9 ns (was 0 ticks) 8 ns GPMC CS1: cs_rd_off : 9 ticks, 82 ns (was 5 ticks) 82 ns GPMC CS1: cs_wr_off : 9 ticks, 82 ns (was 5 ticks) 82 ns GPMC CS1: adv_on : 6 ticks, 54 ns (was 0 ticks) 48 ns GPMC CS1: adv_rd_off: 7 ticks, 63 ns (was 3 ticks) 63 ns GPMC CS1: adv_wr_off: 7 ticks, 63 ns (was 3 ticks) 63 ns GPMC CS1: oe_on : 7 ticks, 63 ns (was 4 ticks) 63 ns GPMC CS1: oe_off : 9 ticks, 82 ns (was 5 ticks) 82 ns GPMC CS1: we_on : 8 ticks, 72 ns (was 4 ticks) 72 ns GPMC CS1: we_off : 9 ticks, 82 ns (was 5 ticks) 82 ns GPMC CS1: rd_cycle : 10 ticks, 91 ns (was 5 ticks) 91 ns GPMC CS1: wr_cycle : 10 ticks, 91 ns (was 5 ticks) 91 ns GPMC CS1: access : 8 ticks, 72 ns (was 5 ticks) 72 ns GPMC CS1: page_burst_access: 0 ticks, 0 ns (was 0 ticks) 0 ns GPMC CS1: bus_turnaround: 0 ticks, 0 ns (was 0 ticks) 0 ns GPMC CS1: cycle2cycle_delay: 0 ticks, 0 ns (was 0 ticks) 0 ns GPMC CS1: wait_monitoring: 0 ticks, 0 ns (was 0 ticks) 0 ns GPMC CS1: clk_activation: 0 ticks, 0 ns (was 0 ticks) 0 ns GPMC CS4: cs_on : 1 ticks, 9 ns (was 0 ticks) 8 ns GPMC CS4: cs_rd_off : 16 ticks, 145 ns (was 7 ticks) 145 ns GPMC CS4: cs_wr_off : 16 ticks, 145 ns (was 7 ticks) 144 ns GPMC CS4: adv_on : 6 ticks, 54 ns (was 2 ticks) 48 ns GPMC CS4: adv_rd_off: 7 ticks, 63 ns (was 4 ticks) 63 ns GPMC CS4: adv_wr_off: 7 ticks, 63 ns (was 4 ticks) 63 ns GPMC CS4: oe_on : 10 ticks, 91 ns (was 5 ticks) 90 ns GPMC CS4: oe_off : 16 ticks, 145 ns (was 7 ticks) 145 ns GPMC CS4: we_on : 10 ticks, 91 ns (was 5 ticks) 90 ns GPMC CS4: we_off : 16 ticks, 145 ns (was 6 ticks) 144 ns GPMC CS4: rd_cycle : 17 ticks, 154 ns (was 8 ticks) 154 ns GPMC CS4: wr_cycle : 17 ticks, 154 ns (was 8 ticks) 154 ns GPMC CS4: access : 15 ticks, 136 ns (was 6 ticks) 135 ns GPMC CS4: page_burst_access: 2 ticks, 18 ns (was 2 ticks) 18 ns GPMC CS4: bus_turnaround: 0 ticks, 0 ns (was 0 ticks) 0 ns GPMC CS4: cycle2cycle_delay: 0 ticks, 0 ns (was 0 ticks) 0 ns GPMC CS4: wait_monitoring: 0 ticks, 0 ns (was 0 ticks) 0 ns GPMC CS4: clk_activation: 1 ticks, 9 ns (was 0 ticks) 9 ns GPMC CS4 CLK period is 18 ns (div 2) TUSB 6010 ... OneNAND driver initializing GPMC CS0: cs_on : 0 ticks, 0 ns (was 0 ticks) 0 ns GPMC CS0: cs_rd_off : 10 ticks, 91 ns (was 12 ticks) 91 ns GPMC CS0: cs_wr_off : 12 ticks, 109 ns (was 9 ticks) 108 ns GPMC CS0: adv_on : 0 ticks, 0 ns (was 0 ticks) 0 ns GPMC CS0: adv_rd_off: 2 ticks, 18 ns (was 2 ticks) 18 ns GPMC CS0: adv_wr_off: 2 ticks, 18 ns (was 2 ticks) 18 ns GPMC CS0: oe_on : 3 ticks, 27 ns (was 2 ticks) 27 ns GPMC CS0: oe_off : 10 ticks, 91 ns (was 12 ticks) 91 ns GPMC CS0: we_on : 3 ticks, 27 ns (was 3 ticks) 27 ns GPMC CS0: we_off : 8 ticks, 72 ns (was 8 ticks) 72 ns GPMC CS0: rd_cycle : 13 ticks, 118 ns (was 13 ticks) 118 ns GPMC CS0: wr_cycle : 15 ticks, 136 ns (was 10 ticks) 135 ns GPMC CS0: access : 9 ticks, 82 ns (was 11 ticks) 82 ns GPMC CS0: page_burst_access: 0 ticks, 0 ns (was 2 ticks) 0 ns GPMC CS0: bus_turnaround: 0 ticks, 0 ns (was 0 ticks) 0 ns GPMC CS0: cycle2cycle_delay: 0 ticks, 0 ns (was 0 ticks) 0 ns GPMC CS0: wait_monitoring: 0 ticks, 0 ns (was 0 ticks) 0 ns GPMC CS0: clk_activation: 0 ticks, 0 ns (was 0 ticks) 0 ns GPMC CS0: cs_on : 0 ticks, 0 ns (was 0 ticks) 0 ns GPMC CS0: cs_rd_off : 14 ticks, 127 ns (was 10 ticks) 127 ns GPMC CS0: cs_wr_off : 12 ticks, 109 ns (was 12 ticks) 108 ns GPMC CS0: adv_on : 0 ticks, 0 ns (was 0 ticks) 0 ns GPMC CS0: adv_rd_off: 2 ticks, 18 ns (was 2 ticks) 18 ns GPMC CS0: adv_wr_off: 2 ticks, 18 ns (was 2 ticks) 18 ns GPMC CS0: oe_on : 3 ticks, 27 ns (was 3 ticks) 27 ns GPMC CS0: oe_off : 14 ticks, 127 ns (was 10 ticks) 127 ns GPMC CS0: we_on : 3 ticks, 27 ns (was 3 ticks) 27 ns GPMC CS0: we_off : 8 ticks, 72 ns (was 8 ticks) 72 ns GPMC CS0: rd_cycle : 16 ticks, 145 ns (was 13 ticks) 145 ns GPMC CS0: wr_cycle : 15 ticks, 136 ns (was 15 ticks) 135 ns GPMC CS0: access : 13 ticks, 118 ns (was 9 ticks) 118 ns GPMC CS0: page_burst_access: 3 ticks, 27 ns (was 0 ticks) 27 ns GPMC CS0: bus_turnaround: 0 ticks, 0 ns (was 0 ticks) 0 ns GPMC CS0: cycle2cycle_delay: 0 ticks, 0 ns (was 0 ticks) 0 ns GPMC CS0: wait_monitoring: 0 ticks, 0 ns (was 0 ticks) 0 ns GPMC CS0: clk_activation: 1 ticks, 9 ns (was 0 ticks) 9 ns GPMC CS0 CLK period is 27 ns (div 3) omap2-onenand omap2-onenand: initializing on CS0, phys base 0x04000000, virtual base c88c0000, freq 54 MHz OneNAND Manufacturer: Samsung (0xec) Muxed OneNAND(DDP) 256MB 1.8V 16-bit (0x48) OneNAND version = 0x0011 Chip support all block unlock onenand_wait: controller error! state 15 ctrl 0x0400 intr 0x8000 Scanning device for bad blocks Creating 5 MTD partitions on "omap2-onenand": 0x000000000000-0x000000020000 : "bootloader" 0x000000020000-0x000000080000 : "config" 0x000000080000-0x000000280000 : "kernel" 0x000000280000-0x000000680000 : "initfs" 0x000000680000-0x000010000000 : "rootfs" omap-dma-engine omap-dma-engine: allocating channel for 44 omap-dma-engine omap-dma-engine: allocating channel for 43
Hi Tony, On Wed, Sep 12, 2012 at 00:16:06, Tony Lindgren wrote: > Here are the timing changes with and without this patch from > my n800. You can just diff the two files to see some differences. Hmm.. that was pretty close, OneNAND async,sync as well as tusb sync values were same. But some of the tusb async values is less by one. I need to get it right. And thanks for sending me the easily diff-able logs. Regards Afzal
diff --git a/arch/arm/mach-omap2/usb-tusb6010.c b/arch/arm/mach-omap2/usb-tusb6010.c index 7a85ebe..cce1f06 100644 --- a/arch/arm/mach-omap2/usb-tusb6010.c +++ b/arch/arm/mach-omap2/usb-tusb6010.c @@ -26,182 +26,87 @@ static u8 async_cs, sync_cs; static unsigned refclk_psec; -/* t2_ps, when quantized to fclk units, must happen no earlier than - * the clock after after t1_NS. - * - * Return a possibly updated value of t2_ps, converted to nsec. - */ -static unsigned -next_clk(unsigned t1_NS, unsigned t2_ps, unsigned fclk_ps) -{ - unsigned t1_ps = t1_NS * 1000; - unsigned t1_f, t2_f; - - if ((t1_ps + fclk_ps) < t2_ps) - return t2_ps / 1000; - - t1_f = (t1_ps + fclk_ps - 1) / fclk_ps; - t2_f = (t2_ps + fclk_ps - 1) / fclk_ps; - - if (t1_f >= t2_f) - t2_f = t1_f + 1; - - return (t2_f * fclk_ps) / 1000; -} - /* NOTE: timings are from tusb 6010 datasheet Rev 1.8, 12-Sept 2006 */ -static int tusb_set_async_mode(unsigned sysclk_ps, unsigned fclk_ps) +static int tusb_set_async_mode(unsigned sysclk_ps) { + struct gpmc_device_timings dev_t; struct gpmc_timings t; unsigned t_acsnh_advnh = sysclk_ps + 3000; - unsigned tmp; - - memset(&t, 0, sizeof(t)); - - /* CS_ON = t_acsnh_acsnl */ - t.cs_on = 8; - /* ADV_ON = t_acsnh_advnh - t_advn */ - t.adv_on = next_clk(t.cs_on, t_acsnh_advnh - 7000, fclk_ps); - - /* - * READ ... from omap2420 TRM fig 12-13 - */ - - /* ADV_RD_OFF = t_acsnh_advnh */ - t.adv_rd_off = next_clk(t.adv_on, t_acsnh_advnh, fclk_ps); - - /* OE_ON = t_acsnh_advnh + t_advn_oen (then wait for nRDY) */ - t.oe_on = next_clk(t.adv_on, t_acsnh_advnh + 1000, fclk_ps); - - /* ACCESS = counters continue only after nRDY */ - tmp = t.oe_on * 1000 + 300; - t.access = next_clk(t.oe_on, tmp, fclk_ps); - - /* OE_OFF = after data gets sampled */ - tmp = t.access * 1000; - t.oe_off = next_clk(t.access, tmp, fclk_ps); - - t.cs_rd_off = t.oe_off; - - tmp = t.cs_rd_off * 1000 + 7000 /* t_acsn_rdy_z */; - t.rd_cycle = next_clk(t.cs_rd_off, tmp, fclk_ps); - - /* - * WRITE ... from omap2420 TRM fig 12-15 - */ - /* ADV_WR_OFF = t_acsnh_advnh */ - t.adv_wr_off = t.adv_rd_off; + memset(&dev_t, 0, sizeof(dev_t)); - /* WE_ON = t_acsnh_advnh + t_advn_wen (then wait for nRDY) */ - t.we_on = next_clk(t.adv_wr_off, t_acsnh_advnh + 1000, fclk_ps); + dev_t.mux = true; - /* WE_OFF = after data gets sampled */ - tmp = t.we_on * 1000 + 300; - t.we_off = next_clk(t.we_on, tmp, fclk_ps); + dev_t.t_ceasu = 8 * 1000; + dev_t.t_avdasu = t_acsnh_advnh - 7000; + dev_t.t_ce_avd = 1000; + dev_t.t_avdp_r = t_acsnh_advnh; + dev_t.t_oeasu = t_acsnh_advnh + 1000; + dev_t.t_oe = 300; + dev_t.t_cez_r = dev_t.t_cez_w = 7000; + dev_t.t_avdp_w = t_acsnh_advnh; + dev_t.t_weasu = t_acsnh_advnh + 1000; + dev_t.t_wpl = 300; + dev_t.cyc_aavdh_we = 1; - t.cs_wr_off = t.we_off; - - tmp = t.cs_wr_off * 1000 + 7000 /* t_acsn_rdy_z */; - t.wr_cycle = next_clk(t.cs_wr_off, tmp, fclk_ps); + gpmc_calc_timings(&t, &dev_t); return gpmc_cs_set_timings(async_cs, &t); } -static int tusb_set_sync_mode(unsigned sysclk_ps, unsigned fclk_ps) +static int tusb_set_sync_mode(unsigned sysclk_ps) { + struct gpmc_device_timings dev_t; struct gpmc_timings t; unsigned t_scsnh_advnh = sysclk_ps + 3000; - unsigned tmp; - - memset(&t, 0, sizeof(t)); - t.cs_on = 8; - - /* ADV_ON = t_acsnh_advnh - t_advn */ - t.adv_on = next_clk(t.cs_on, t_scsnh_advnh - 7000, fclk_ps); - - /* GPMC_CLK rate = fclk rate / div */ - t.sync_clk = 11100 /* 11.1 nsec */; - tmp = (t.sync_clk + fclk_ps - 1) / fclk_ps; - if (tmp > 4) - return -ERANGE; - if (tmp == 0) - tmp = 1; - t.page_burst_access = (fclk_ps * tmp) / 1000; - - /* - * READ ... based on omap2420 TRM fig 12-19, 12-20 - */ - - /* ADV_RD_OFF = t_scsnh_advnh */ - t.adv_rd_off = next_clk(t.adv_on, t_scsnh_advnh, fclk_ps); - - /* OE_ON = t_scsnh_advnh + t_advn_oen * fclk_ps (then wait for nRDY) */ - tmp = (t.adv_rd_off * 1000) + (3 * fclk_ps); - t.oe_on = next_clk(t.adv_on, tmp, fclk_ps); - - /* ACCESS = number of clock cycles after t_adv_eon */ - tmp = (t.oe_on * 1000) + (5 * fclk_ps); - t.access = next_clk(t.oe_on, tmp, fclk_ps); - - /* OE_OFF = after data gets sampled */ - tmp = (t.access * 1000) + (1 * fclk_ps); - t.oe_off = next_clk(t.access, tmp, fclk_ps); - t.cs_rd_off = t.oe_off; - - tmp = t.cs_rd_off * 1000 + 7000 /* t_scsn_rdy_z */; - t.rd_cycle = next_clk(t.cs_rd_off, tmp, fclk_ps); - - /* - * WRITE ... based on omap2420 TRM fig 12-21 - */ - - /* ADV_WR_OFF = t_scsnh_advnh */ - t.adv_wr_off = t.adv_rd_off; - - /* WE_ON = t_scsnh_advnh + t_advn_wen * fclk_ps (then wait for nRDY) */ - tmp = (t.adv_wr_off * 1000) + (3 * fclk_ps); - t.we_on = next_clk(t.adv_wr_off, tmp, fclk_ps); - - /* WE_OFF = number of clock cycles after t_adv_wen */ - tmp = (t.we_on * 1000) + (6 * fclk_ps); - t.we_off = next_clk(t.we_on, tmp, fclk_ps); - - t.cs_wr_off = t.we_off; - - tmp = t.cs_wr_off * 1000 + 7000 /* t_scsn_rdy_z */; - t.wr_cycle = next_clk(t.cs_wr_off, tmp, fclk_ps); - - t.clk_activation = gpmc_ticks_to_ns(1); + memset(&dev_t, 0, sizeof(dev_t)); + + dev_t.mux = true; + dev_t.sync_read = true; + dev_t.sync_write = true; + + dev_t.clk = 11100; + dev_t.t_bacc = 1000; + dev_t.t_ces = 1000; + dev_t.t_ceasu = 8 * 1000; + dev_t.t_avdasu = t_scsnh_advnh - 7000; + dev_t.t_ce_avd = 1000; + dev_t.t_avdp_r = t_scsnh_advnh; + dev_t.cyc_aavdh_oe = 3; + dev_t.cyc_oe = 5; + dev_t.t_ce_rdyz = 7000; + dev_t.t_avdp_w = t_scsnh_advnh; + dev_t.cyc_aavdh_we = 3; + dev_t.cyc_wpl = 6; + dev_t.t_ce_rdyz = 7000; + + gpmc_calc_timings(&t, &dev_t); return gpmc_cs_set_timings(sync_cs, &t); } -extern unsigned long gpmc_get_fclk_period(void); - /* tusb driver calls this when it changes the chip's clocking */ int tusb6010_platform_retime(unsigned is_refclk) { static const char error[] = KERN_ERR "tusb6010 %s retime error %d\n"; - unsigned fclk_ps = gpmc_get_fclk_period(); unsigned sysclk_ps; int status; - if (!refclk_psec || fclk_ps == 0) + if (!refclk_psec) return -ENODEV; sysclk_ps = is_refclk ? refclk_psec : TUSB6010_OSCCLK_60; - status = tusb_set_async_mode(sysclk_ps, fclk_ps); + status = tusb_set_async_mode(sysclk_ps); if (status < 0) { printk(error, "async", status); goto done; } - status = tusb_set_sync_mode(sysclk_ps, fclk_ps); + status = tusb_set_sync_mode(sysclk_ps); if (status < 0) printk(error, "sync", status); done:
Generic gpmc timing calculation helper is available now, use it instead of custom timing calculation. Signed-off-by: Afzal Mohammed <afzal@ti.com> --- arch/arm/mach-omap2/usb-tusb6010.c | 181 +++++++++--------------------------- 1 files changed, 43 insertions(+), 138 deletions(-)