From patchwork Wed Feb 11 08:16:24 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 5810721 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 1353E9F39D for ; Wed, 11 Feb 2015 08:19:42 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id BD39320107 for ; Wed, 11 Feb 2015 08:19:40 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 798BE200F3 for ; Wed, 11 Feb 2015 08:19:39 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YLSUC-0003G1-Bi; Wed, 11 Feb 2015 08:17:28 +0000 Received: from mail-pa0-f43.google.com ([209.85.220.43]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1YLSU3-0003BH-HN for linux-arm-kernel@lists.infradead.org; Wed, 11 Feb 2015 08:17:21 +0000 Received: by mail-pa0-f43.google.com with SMTP id fa1so2542596pad.2 for ; Wed, 11 Feb 2015 00:16:58 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=oY5939y+fEHl17wMVFzFDR8UdOxAc34yGfYmZcvSSjg=; b=Fa0lpuBEhu7r6siL4vxePwz4hu9wRFOz/qP/UuJkhmq2M/3+ABOK8WWsmdv5kUUuAy +122sxtEmERkl+rLCUw7U6jNAR9MLla0YEwTSfDfIJ6xVaCHC/YcZiR7O5yVXskARMZp tF8whStf76gpW7/brNjsKKhxEczyi2Horu576f7pAt50Iu67ADKS6aYXDXJJfYgDpHBz lQUZBtHuwVuRIHuttw52KvD2dqxtok9m2oQ5xPLIYPhHns7YgwBf6GkKY7arV8kYw3DT QUVSstCqF4RNg007QlUcWTl3EtVWcXPBi7UBGJu2eOasv1tDgtVsjG9mfIwbFkW0mDs8 fodA== X-Gm-Message-State: ALoCoQmGlcUmYHYmcdpjQhTRiH45eIeiJi/H8feRXFFqoVzQkyl1kf5vPj/oBcVqtnCmRrMosFu8 X-Received: by 10.68.200.201 with SMTP id ju9mr31025171pbc.157.1423642617205; Wed, 11 Feb 2015 00:16:57 -0800 (PST) Received: from localhost ([210.177.145.249]) by mx.google.com with ESMTPSA id ff10sm181950pad.1.2015.02.11.00.16.55 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Wed, 11 Feb 2015 00:16:56 -0800 (PST) From: Viresh Kumar To: Rafael Wysocki , rob.herring@linaro.org Subject: [PATCH 1/7] OPP: Redefine bindings to overcome shortcomings Date: Wed, 11 Feb 2015 16:16:24 +0800 Message-Id: X-Mailer: git-send-email 2.3.0.rc0.44.ga94655d In-Reply-To: References: In-Reply-To: References: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150211_001719_702709_FC134231 X-CRM114-Status: GOOD ( 12.84 ) X-Spam-Score: -0.7 (/) Cc: nm@ti.com, devicetree@vger.kernel.org, kesavan.abhilash@gmail.com, linaro-kernel@lists.linaro.org, ta.omasab@gmail.com, linux-pm@vger.kernel.org, viswanath.puttagunta@linaro.org, catalin.marinas@arm.com, santosh.shilimkar@oracle.com, sboyd@codeaurora.org, olof@lixom.net, broonie@kernel.org, Viresh Kumar , mike.turquette@linaro.org, Sudeep.Holla@arm.com, grant.likely@linaro.org, arnd.bergmann@linaro.org, thomas.petazzoni@free-electrons.com, linux-arm-kernel@lists.infradead.org, l.stach@pengutronix.de X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Current OPP (Operating performance point) DT bindings are proven to be insufficient at multiple instances. There had been multiple band-aid approaches to get them fixed (The latest one being: http://www.mail-archive.com/devicetree@vger.kernel.org/msg53398.html). For obvious reasons Rob rejected them and shown the right path forward. The shortcomings we are trying to solve here: - Getting clock sharing information between CPUs. Single shared clock vs independent clock per core vs shared clock per cluster. - Support for turbo modes - Support for intermediate frequencies or OPPs we can switch to. - Other per OPP settings: transition latencies, disabled status, etc.? - Expandability of OPPs in future. This patch introduces new bindings "operating-points-v2" to get these problems solved. Refer to the bindings for more details. Signed-off-by: Viresh Kumar --- Documentation/devicetree/bindings/power/opp.txt | 407 +++++++++++++++++++++++- 1 file changed, 403 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/power/opp.txt b/Documentation/devicetree/bindings/power/opp.txt index 74499e5033fc..a64621819d7c 100644 --- a/Documentation/devicetree/bindings/power/opp.txt +++ b/Documentation/devicetree/bindings/power/opp.txt @@ -1,8 +1,407 @@ -* Generic OPP Interface +Generic OPP (Operating Performance Points) Bindings +---------------------------------------------------- -SoCs have a standard set of tuples consisting of frequency and -voltage pairs that the device will support per voltage domain. These -are called Operating Performance Points or OPPs. +Devices work at voltage-frequency pairs and some implementations have the +liberty of choosing these pairs. These pairs are called Operating Performance +Points aka OPPs. This document defines bindings for these OPPs applicable across +wide range of devices. For illustration purpose, this document uses CPU as a +device. + + +* Property: operating-points-v2 + +Devices supporting OPPs must set their "operating-points-v2" property with +phandle to a OPP descriptor in their DT node. The OPP core will use this phandle +to find the operating points for the device. + + +* OPP Descriptor Node + +This describes the OPPs belonging to a device. This node can have following +properties: + +Required properties: +- compatible: Allow OPPs to express their compatibility. It should be: + "operating-points-v2". +- OPP nodes: One or more OPP nodes describing frequency-voltage pairs. Their + name isn't significant but their phandles can be used to reference an OPP. + +Optional properties: +- shared-opp: Indicates that device nodes using this OPP descriptor's phandle + switch their DVFS state together, i.e. they share clock lines. Missing + property means devices have independent clock lines, but they share OPPs. + + +* OPP Node + +This defines frequency-voltage pairs along with other related properties. + +Required properties: +- opp-khz: Frequency in kHz + +Optional properties: +- opp-microvolt: voltage in micro Volts. Its an array with size one or three. + Single entry is for target voltage and three entries are for (in the specified + order) voltage. +- clock-latency-ns: Specifies the maximum possible transition latency (in + nanoseconds) for switching to this OPP from any other OPP. +- opp-next: It contains a list of phandles of other OPPs, to which we can switch + directly from this OPP (Explained later with examples). Missing property means + no restriction on switching to other OPPs. +- turbo-mode: Marks the OPP to be used only for turbo modes. +- status: Marks the node enabled/disabled. + +Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states together. + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a9"; + reg = <0>; + next-level-cache = <&L2>; + clocks = <&clk_controller 0>; + clock-names = "cpu"; + opp-supply = <&cpu_supply0>; + operating-points-v2 = <&cpu0_opp>; + }; + + cpu@1 { + compatible = "arm,cortex-a9"; + reg = <1>; + next-level-cache = <&L2>; + clocks = <&clk_controller 0>; + clock-names = "cpu"; + opp-supply = <&cpu_supply0>; + operating-points-v2 = <&cpu0_opp>; + }; + }; + + cpu0_opp: opp0 { + compatible = "operating-points-v2"; + shared-opp; + + entry00 { + opp-khz = <1000000>; + opp-microvolt = <970000 975000 985000>; + clock-latency-ns = <300000>; + }; + entry01 { + opp-khz = <1100000>; + opp-microvolt = <980000 1000000 1010000>; + clock-latency-ns = <310000>; + }; + entry02 { + opp-khz = <1200000>; + opp-microvolt = <1025000>; + clock-latency-ns = <290000>; + turbo-mode; + }; + }; +}; + +Example 2: Single cluster, Quad-core Qualcom-krait, switches DVFS states +independently. + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "qcom,krait"; + reg = <0>; + next-level-cache = <&L2>; + clocks = <&clk_controller 0>; + clock-names = "cpu"; + opp-supply = <&cpu_supply0>; + operating-points-v2 = <&cpu0_opp>; + }; + + cpu@1 { + compatible = "qcom,krait"; + reg = <1>; + next-level-cache = <&L2>; + clocks = <&clk_controller 1>; + clock-names = "cpu"; + opp-supply = <&cpu_supply1>; + operating-points-v2 = <&cpu0_opp>; + }; + + cpu@2 { + compatible = "qcom,krait"; + reg = <2>; + next-level-cache = <&L2>; + clocks = <&clk_controller 2>; + clock-names = "cpu"; + opp-supply = <&cpu_supply2>; + operating-points-v2 = <&cpu0_opp>; + }; + + cpu@3 { + compatible = "qcom,krait"; + reg = <3>; + next-level-cache = <&L2>; + clocks = <&clk_controller 3>; + clock-names = "cpu"; + opp-supply = <&cpu_supply3>; + operating-points-v2 = <&cpu0_opp>; + }; + }; + + cpu0_opp: opp0 { + compatible = "operating-points-v2"; + + /* + * Missing shared-opp property means CPUs switch DVFS states + * independently. + */ + + entry00 { + opp-khz = <1000000>; + opp-microvolt = <970000 975000 985000>; + clock-latency-ns = <300000>; + }; + entry01 { + opp-khz = <1100000>; + opp-microvolt = <980000 1000000 1010000>; + clock-latency-ns = <310000>; + }; + entry02 { + opp-khz = <1200000>; + opp-microvolt = <1025000>; + clock-latency-ns = <290000>; + turbo-mode; + }; + }; +}; + +Example 3: Dual-cluster, Dual-core per cluster. CPUs within a cluster switch +DVFS state together. + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a7"; + reg = <0>; + next-level-cache = <&L2>; + clocks = <&clk_controller 0>; + clock-names = "cpu"; + opp-supply = <&cpu_supply0>; + operating-points-v2 = <&cluster0_opp>; + }; + + cpu@1 { + compatible = "arm,cortex-a7"; + reg = <1>; + next-level-cache = <&L2>; + clocks = <&clk_controller 0>; + clock-names = "cpu"; + opp-supply = <&cpu_supply0>; + operating-points-v2 = <&cluster0_opp>; + }; + + cpu@100 { + compatible = "arm,cortex-a15"; + reg = <100>; + next-level-cache = <&L2>; + clocks = <&clk_controller 1>; + clock-names = "cpu"; + opp-supply = <&cpu_supply1>; + operating-points-v2 = <&cluster1_opp>; + }; + + cpu@101 { + compatible = "arm,cortex-a15"; + reg = <101>; + next-level-cache = <&L2>; + clocks = <&clk_controller 1>; + clock-names = "cpu"; + opp-supply = <&cpu_supply1>; + operating-points-v2 = <&cluster1_opp>; + }; + }; + + cluster0_opp: opp0 { + compatible = "operating-points-v2"; + shared-opp; + + entry00 { + opp-khz = <1000000>; + opp-microvolt = <970000 975000 985000>; + clock-latency-ns = <300000>; + }; + entry01 { + opp-khz = <1100000>; + opp-microvolt = <980000 1000000 1010000>; + clock-latency-ns = <310000>; + }; + entry02 { + opp-khz = <1200000>; + opp-microvolt = <1025000>; + clock-latency-ns = <290000>; + turbo-mode; + }; + }; + + cluster1_opp: opp1 { + compatible = "operating-points-v2"; + shared-opp; + + entry10 { + opp-khz = <1300000>; + opp-microvolt = <1045000 1050000 1055000>; + clock-latency-ns = <400000>; + }; + entry11 { + opp-khz = <1400000>; + opp-microvolt = <1075000>; + clock-latency-ns = <400000>; + }; + entry12 { + opp-khz = <1500000>; + opp-microvolt = <1010000 1100000 1110000>; + clock-latency-ns = <400000>; + turbo-mode; + }; + }; +}; + +Example 4: How to use "opp-next" property ? + +1.) Switch to a intermediate OPP (entry00) before switching to any other OPP. + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a7"; + reg = <0>; + next-level-cache = <&L2>; + clocks = <&clk_controller 0>; + clock-names = "cpu"; + opp-supply = <&cpu_supply0>; + operating-points-v2 = <&cpu0_opp>; + }; + }; + + cpu0_opp: opp0 { + compatible = "operating-points-v2"; + shared-opp; + + opp_next: entry00 { + opp-khz = <500000>; + opp-microvolt = <800000>; + clock-latency-ns = <300000>; + /* Can switch to any OPP from here */ + }; + entry01 { + opp-khz = <600000>; + opp-microvolt = <800000>; + clock-latency-ns = <300000>; + opp-next = <&opp_next>; + }; + entry02 { + opp-khz = <900000>; + opp-microvolt = <970000 975000 985000>; + clock-latency-ns = <300000>; + opp-next = <&opp_next>; + }; + entry03 { + opp-khz = <1000000>; + opp-microvolt = <970000 975000 985000>; + clock-latency-ns = <300000>; + opp-next = <&opp_next>; + }; + entry04 { + opp-khz = <1100000>; + opp-microvolt = <980000 1000000 1010000>; + clock-latency-ns = <310000>; + opp-next = <&opp_next>; + }; + entry05 { + opp-khz = <1200000>; + opp-microvolt = <1025000>; + clock-latency-ns = <290000>; + opp-next = <&opp_next>; + turbo-mode; + }; + }; +}; + +2.) Can only switch to the next or previous OPP directly. + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a7"; + reg = <0>; + next-level-cache = <&L2>; + clocks = <&clk_controller 0>; + clock-names = "cpu"; + opp-supply = <&cpu_supply0>; + operating-points-v2 = <&cpu0_opp>; + }; + }; + + cpu0_opp: opp0 { + compatible = "operating-points-v2"; + shared-opp; + + opp_next0: entry00 { + opp-khz = <500000>; + opp-microvolt = <800000>; + clock-latency-ns = <300000>; + opp-next = <&opp_next1>; + }; + opp_next1: entry01 { + opp-khz = <600000>; + opp-microvolt = <800000>; + clock-latency-ns = <300000>; + opp-next = <&opp_next0>, <&opp_next2>; + }; + opp_next2: entry02 { + opp-khz = <900000>; + opp-microvolt = <970000 975000 985000>; + clock-latency-ns = <300000>; + opp-next = <&opp_next1>, <&opp_next3>; + }; + opp_next3: entry03 { + opp-khz = <1000000>; + opp-microvolt = <970000 975000 985000>; + clock-latency-ns = <300000>; + opp-next = <&opp_next2>, <&opp_next4>; + }; + opp_next4: entry04 { + opp-khz = <1100000>; + opp-microvolt = <980000 1000000 1010000>; + clock-latency-ns = <310000>; + opp-next = <&opp_next3>, <&opp_next5>; + }; + opp_next5: entry05 { + opp-khz = <1200000>; + opp-microvolt = <1025000>; + clock-latency-ns = <290000>; + opp-next = <&opp_next4>; + turbo-mode; + }; + }; +}; + + + +Deprecated Bindings +------------------- Properties: - operating-points: An array of 2-tuples items, and each item consists