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[178.255.168.35]) by smtp.gmail.com with ESMTPSA id i13sm1284622ejc.57.2020.12.02.06.06.22 (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 02 Dec 2020 06:06:22 -0800 (PST) From: Michal Simek To: linux-kernel@vger.kernel.org, monstr@monstr.eu, michal.simek@xilinx.com, git@xilinx.com Subject: [PATCH 04/12] arm64: dts: zynqmp: Enable and wire reset controller Date: Wed, 2 Dec 2020 15:06:03 +0100 Message-Id: X-Mailer: git-send-email 2.29.2 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201202_090625_092604_0F4E0F3F X-CRM114-Status: GOOD ( 12.26 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Rajan Vaja , Krzysztof Kozlowski , Rob Herring , Manish Narani , Laurent Pinchart , Kalyani Akula , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Enable reset controller for several IPs. Signed-off-by: Michal Simek --- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 29 ++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 68923fbd0e89..4fa820f78d76 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -187,6 +187,11 @@ zynqmp_pcap: pcap { xlnx_aes: zynqmp-aes { compatible = "xlnx,zynqmp-aes"; }; + + zynqmp_reset: reset-controller { + compatible = "xlnx,zynqmp-reset"; + #reset-cells = <1>; + }; }; }; @@ -466,6 +471,8 @@ gem0: ethernet@ff0b0000 { #address-cells = <1>; #size-cells = <0>; power-domains = <&zynqmp_firmware PD_ETH_0>; + resets = <&zynqmp_reset ZYNQMP_RESET_GEM0>; + reset-names = "gem0_rst"; }; gem1: ethernet@ff0c0000 { @@ -478,6 +485,8 @@ gem1: ethernet@ff0c0000 { #address-cells = <1>; #size-cells = <0>; power-domains = <&zynqmp_firmware PD_ETH_1>; + resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>; + reset-names = "gem1_rst"; }; gem2: ethernet@ff0d0000 { @@ -490,6 +499,8 @@ gem2: ethernet@ff0d0000 { #address-cells = <1>; #size-cells = <0>; power-domains = <&zynqmp_firmware PD_ETH_2>; + resets = <&zynqmp_reset ZYNQMP_RESET_GEM2>; + reset-names = "gem2_rst"; }; gem3: ethernet@ff0e0000 { @@ -502,6 +513,8 @@ gem3: ethernet@ff0e0000 { #address-cells = <1>; #size-cells = <0>; power-domains = <&zynqmp_firmware PD_ETH_3>; + resets = <&zynqmp_reset ZYNQMP_RESET_GEM3>; + reset-names = "gem3_rst"; }; gpio: gpio@ff0a0000 { @@ -515,6 +528,8 @@ gpio: gpio@ff0a0000 { #interrupt-cells = <2>; reg = <0x0 0xff0a0000 0x0 0x1000>; power-domains = <&zynqmp_firmware PD_GPIO>; + resets = <&zynqmp_reset ZYNQMP_RESET_GPIO>; + reset-names = "gpio_rst"; }; i2c0: i2c@ff020000 { @@ -526,6 +541,8 @@ i2c0: i2c@ff020000 { #address-cells = <1>; #size-cells = <0>; power-domains = <&zynqmp_firmware PD_I2C_0>; + resets = <&zynqmp_reset ZYNQMP_RESET_I2C0>; + reset-names = "i2c0_rst"; }; i2c1: i2c@ff030000 { @@ -537,6 +554,8 @@ i2c1: i2c@ff030000 { #address-cells = <1>; #size-cells = <0>; power-domains = <&zynqmp_firmware PD_I2C_1>; + resets = <&zynqmp_reset ZYNQMP_RESET_I2C1>; + reset-names = "i2c1_rst"; }; pcie: pcie@fd0e0000 { @@ -602,6 +621,8 @@ sata: ahci@fd0c0000 { interrupt-parent = <&gic>; interrupts = <0 133 4>; power-domains = <&zynqmp_firmware PD_SATA>; + resets = <&zynqmp_reset ZYNQMP_RESET_SATA>; + reset-names = "sata_rst"; }; sdhci0: mmc@ff160000 { @@ -733,6 +754,10 @@ usb0: usb@fe200000 { reg = <0x0 0xfe200000 0x0 0x40000>; clock-names = "clk_xin", "clk_ahb"; power-domains = <&zynqmp_firmware PD_USB_0>; + resets = <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>, + <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>, + <&zynqmp_reset ZYNQMP_RESET_USB0_APB>; + reset-names = "usb0_crst", "usb0_hibrst", "usb0_apbrst"; }; usb1: usb@fe300000 { @@ -743,6 +768,10 @@ usb1: usb@fe300000 { reg = <0x0 0xfe300000 0x0 0x40000>; clock-names = "clk_xin", "clk_ahb"; power-domains = <&zynqmp_firmware PD_USB_1>; + resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>, + <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>, + <&zynqmp_reset ZYNQMP_RESET_USB1_APB>; + reset-names = "usb1_crst", "usb1_hibrst", "usb1_apbrst"; }; watchdog0: watchdog@fd4d0000 {