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Tue, 27 Aug 2024 10:01:36 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , , , Subject: [PATCH v2 05/19] iommufd/selftest: Add IOMMU_VIOMMU_ALLOC test coverage Date: Tue, 27 Aug 2024 09:59:42 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9CD:EE_|SJ2PR12MB7896:EE_ X-MS-Office365-Filtering-Correlation-Id: b86d6145-9f75-49c6-e149-08dcc6b9f0b3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|82310400026|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: FOMEbk3Jpdis8N/t3MUwZoNBo09yw9vkZ9jT04MAkfFnWhutMqQC04QGc8ODb2DnxGG91TM+ZBxZDwLgwDTvu5HEY9lC7fpT16kT9bjyc0cIhVBqqSm2QjOj79aYj13Avp1uStxdd+8oS7oR8mXqMOW0HXQZyWymIdbkd1AcdzYMHMVkUrJg+5oaKIE6FmNWgcu6vdRJ4Ji07R9cMny51X4I3CN4bZEsmNmNWIHMH9NnlFWyj5wirx+FVCSwaiZd7h9UXPTo/RIIqrgV0nfxQK6xgQCp8Ge9UiRsrBoIy+8nXm5iFb7mFHHzF2nn7hyc6dU779pfLOAKfXTb6ffdugQZAwRJfq3/yeWpSqb9Fst0FrEr139J6P/PPQFmS0ywj4SalvU9Pu+N+PTjojgHMKQ+u/JOudsq6trtxdCwy+K4XowqjmwgyuPUVVzE0Mvt0w+E5zLE0EFcOcqjhtYPFImqjx2VIn62MO6R5/hQDSs0PBHDRvhU2TAcaXna11x6Pn/Vc/akOasyYo9GwtC5a9sftgEpt8syJNrkK++0ItX5oyAFvA0zrxAppr4GlJkkpY4WnkpfatBiIVzrS+E81ffZAEwECiP7aXr3msPFMzGFZlg8CPLhPU4+l0d4G3KX8w8a3juSKb6+Rxq8gtDcgRY9rBqqA9Ky/j1zKAx7r1ZSl64o+RJHGMEX51RVe1IOonOD0ZBPyhGtypw9C6XhTxDeTot3s6nMgSqLMVcfMH/7OkAMD/ZU1kB8/ND0tIvOtRCMo1ChCqsyZo7a7eOoz8g7+SC+wuAk6LEGAnMZv77u9vMbVH98qInB+tBLJW879XUvEQ0qnZ7lJ9s502aUXe8PVwNASYAVi9uo1q9TLWeuFghI9zg4eS7auhkDrXfwkB3H+PXKPMqYOJz4xkW4p0M9gCCkdgK78Tq7G/5P+LwA9NeZcVh8JXwaDKQQo8W+Lb/pmcX5n+37AD1Zht92lPh62fEd0t4RV7BcF87HGKwBm0iTK84V1cvwW+3R2vsgKgnfgjQ4io8XisvPhkT9ctmFDh+6UHmM2cponJehEIjPtliat1uyyRf5Rtad4TI7JpRpPD+UTmCHO/iVlPc2xF9BZR0YN2pyhBFfcmm3/DMhwLaGDPBZPQFyWz7Ayz3woEG4HyYIIUc0xFYbu0OzS5iWx7jOCctDfQUsgpsHCEZARj3yKF6LITtpbKNtfMPr7P7Xo1JEOOZdHvWc/LTmSJMOyjQGNJQnI9dJx+Y6tQV23ENahuulE1X+jCTdjijVuFkOlvTVtCtP0YDOJlcv37nHsy9QmVjbtyLqrXZpcWxE6M515OJMVs67fk9jdU3B6twSZO/hYMw+YiEnWOp4eT7dmwhY+BuI4bSMPl4NAepiFSI5/xSTWfhF0MQfyqftztMOulSI6IRy5JhGpqJ1YDWikiLBY4QioLb3K5JvhLV62wPK08TUiI/ioD3QkBR2 X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(376014)(82310400026)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Aug 2024 17:01:48.8243 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b86d6145-9f75-49c6-e149-08dcc6b9f0b3 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9CD.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB7896 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240827_100158_391289_0AECE0DF X-CRM114-Status: GOOD ( 13.37 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Use IOMMU_VIOMMU_TYPE_DEFAULT to cover the new IOMMU_VIOMMU_ALLOC ioctl. Signed-off-by: Nicolin Chen --- tools/testing/selftests/iommu/iommufd.c | 35 +++++++++++++++++++ tools/testing/selftests/iommu/iommufd_utils.h | 28 +++++++++++++++ 2 files changed, 63 insertions(+) diff --git a/tools/testing/selftests/iommu/iommufd.c b/tools/testing/selftests/iommu/iommufd.c index 6343f4053bd4..5c770e94f299 100644 --- a/tools/testing/selftests/iommu/iommufd.c +++ b/tools/testing/selftests/iommu/iommufd.c @@ -554,6 +554,41 @@ TEST_F(iommufd_ioas, alloc_hwpt_nested) } } +TEST_F(iommufd_ioas, viommu_default) +{ + uint32_t dev_id = self->device_id; + uint32_t viommu_id = 0; + uint32_t hwpt_id = 0; + + if (dev_id) { + /* Negative test -- invalid hwpt */ + test_err_viommu_alloc(ENOENT, dev_id, hwpt_id, + IOMMU_VIOMMU_TYPE_DEFAULT, &viommu_id); + + /* Negative test -- not a nested parent hwpt */ + test_cmd_hwpt_alloc(dev_id, self->ioas_id, 0, &hwpt_id); + test_err_viommu_alloc(EINVAL, dev_id, hwpt_id, + IOMMU_VIOMMU_TYPE_DEFAULT, &viommu_id); + test_ioctl_destroy(hwpt_id); + + /* Allocate a nested parent HWP */ + test_cmd_hwpt_alloc(dev_id, self->ioas_id, + IOMMU_HWPT_ALLOC_NEST_PARENT, + &hwpt_id); + /* Negative test -- unsupported viommu type */ + test_err_viommu_alloc(EOPNOTSUPP, dev_id, hwpt_id, + 0xdead, &viommu_id); + /* Allocate a default type of viommu */ + test_cmd_viommu_alloc(dev_id, hwpt_id, + IOMMU_VIOMMU_TYPE_DEFAULT, &viommu_id); + test_ioctl_destroy(viommu_id); + test_ioctl_destroy(hwpt_id); + } else { + test_err_viommu_alloc(ENOENT, dev_id, hwpt_id, + IOMMU_VIOMMU_TYPE_DEFAULT, &viommu_id); + } +} + TEST_F(iommufd_ioas, hwpt_attach) { /* Create a device attached directly to a hwpt */ diff --git a/tools/testing/selftests/iommu/iommufd_utils.h b/tools/testing/selftests/iommu/iommufd_utils.h index 40f6f14ce136..307d097db9dd 100644 --- a/tools/testing/selftests/iommu/iommufd_utils.h +++ b/tools/testing/selftests/iommu/iommufd_utils.h @@ -762,3 +762,31 @@ static int _test_cmd_trigger_iopf(int fd, __u32 device_id, __u32 fault_fd) #define test_cmd_trigger_iopf(device_id, fault_fd) \ ASSERT_EQ(0, _test_cmd_trigger_iopf(self->fd, device_id, fault_fd)) + +static int _test_cmd_viommu_alloc(int fd, __u32 device_id, __u32 hwpt_id, + __u32 type, __u32 flags, __u32 *viommu_id) +{ + struct iommu_viommu_alloc cmd = { + .size = sizeof(cmd), + .flags = flags, + .type = type, + .dev_id = device_id, + .hwpt_id = hwpt_id, + }; + int ret; + + ret = ioctl(fd, IOMMU_VIOMMU_ALLOC, &cmd); + if (ret) + return ret; + if (viommu_id) + *viommu_id = cmd.out_viommu_id; + return 0; +} + +#define test_cmd_viommu_alloc(device_id, hwpt_id, type, viommu_id) \ + ASSERT_EQ(0, _test_cmd_viommu_alloc(self->fd, device_id, hwpt_id, \ + type, 0, viommu_id)) +#define test_err_viommu_alloc(_errno, device_id, hwpt_id, type, viommu_id) \ + EXPECT_ERRNO(_errno, _test_cmd_viommu_alloc(self->fd, device_id, \ + hwpt_id, type, 0, \ + viommu_id))