| Message ID | c80eb52e34c03f817586b6b7912fbd4e31be9079.1589475794.git.robin.murphy@arm.com (mailing list archive) |
|---|---|
| State | Mainlined |
| Commit | 465931e70881476a210d44705102ef8b6ee6cdb0 |
| Headers | show |
| Series | [RESEND] Revert "clk: rockchip: fix wrong mmc sample phase shift for rk3328" | expand |
On 2020/6/19 1:56, Robin Murphy wrote: > This reverts commit 82f4b67f018c88a7cc9337f0067ed3d6ec352648. > > According to a subsequent revert in the vendor kernel, the original > change was based on unclear documentation and was in fact incorrect. > Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com> > Emprically, my board's HS200 eMMC at 200MHZ apparently gets lucky with a > phase where this had no impact, but limiting max-frequency to 150MHz to > match the nominal capability of the I/O pins made it virtually unusable, > constantly throwing errors and retuning. With this revert, it starts > behaving perfectly at 150MHz too. > > Fixes: 82f4b67f018c ("clk: rockchip: fix wrong mmc sample phase shift for rk3328") > Signed-off-by: Robin Murphy <robin.murphy@arm.com> > --- > > Resending with the edited commit log I actually meant, rather than the > earlier draft I managed to generate the previuous patch from, since that > one seems to have slipped through the cracks anyway. > > ybetter commit message > drivers/clk/rockchip/clk-rk3328.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/drivers/clk/rockchip/clk-rk3328.c b/drivers/clk/rockchip/clk-rk3328.c > index c186a1985bf4..2429b7c2a8b3 100644 > --- a/drivers/clk/rockchip/clk-rk3328.c > +++ b/drivers/clk/rockchip/clk-rk3328.c > @@ -808,22 +808,22 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = { > MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc", > RK3328_SDMMC_CON0, 1), > MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc", > - RK3328_SDMMC_CON1, 0), > + RK3328_SDMMC_CON1, 1), > > MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio", > RK3328_SDIO_CON0, 1), > MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio", > - RK3328_SDIO_CON1, 0), > + RK3328_SDIO_CON1, 1), > > MMC(SCLK_EMMC_DRV, "emmc_drv", "clk_emmc", > RK3328_EMMC_CON0, 1), > MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "clk_emmc", > - RK3328_EMMC_CON1, 0), > + RK3328_EMMC_CON1, 1), > > MMC(SCLK_SDMMC_EXT_DRV, "sdmmc_ext_drv", "clk_sdmmc_ext", > RK3328_SDMMC_EXT_CON0, 1), > MMC(SCLK_SDMMC_EXT_SAMPLE, "sdmmc_ext_sample", "clk_sdmmc_ext", > - RK3328_SDMMC_EXT_CON1, 0), > + RK3328_SDMMC_EXT_CON1, 1), > }; > > static const char *const rk3328_critical_clocks[] __initconst = { >
On Thu, 18 Jun 2020 18:56:29 +0100, Robin Murphy wrote: > This reverts commit 82f4b67f018c88a7cc9337f0067ed3d6ec352648. > > According to a subsequent revert in the vendor kernel, the original > change was based on unclear documentation and was in fact incorrect. > > Emprically, my board's HS200 eMMC at 200MHZ apparently gets lucky with a > phase where this had no impact, but limiting max-frequency to 150MHz to > match the nominal capability of the I/O pins made it virtually unusable, > constantly throwing errors and retuning. With this revert, it starts > behaving perfectly at 150MHz too. Applied, thanks! [1/1] clk: rockchip: Revert "fix wrong mmc sample phase shift for rk3328" commit: 465931e70881476a210d44705102ef8b6ee6cdb0 Best regards,
diff --git a/drivers/clk/rockchip/clk-rk3328.c b/drivers/clk/rockchip/clk-rk3328.c index c186a1985bf4..2429b7c2a8b3 100644 --- a/drivers/clk/rockchip/clk-rk3328.c +++ b/drivers/clk/rockchip/clk-rk3328.c @@ -808,22 +808,22 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = { MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc", RK3328_SDMMC_CON0, 1), MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc", - RK3328_SDMMC_CON1, 0), + RK3328_SDMMC_CON1, 1), MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio", RK3328_SDIO_CON0, 1), MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio", - RK3328_SDIO_CON1, 0), + RK3328_SDIO_CON1, 1), MMC(SCLK_EMMC_DRV, "emmc_drv", "clk_emmc", RK3328_EMMC_CON0, 1), MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "clk_emmc", - RK3328_EMMC_CON1, 0), + RK3328_EMMC_CON1, 1), MMC(SCLK_SDMMC_EXT_DRV, "sdmmc_ext_drv", "clk_sdmmc_ext", RK3328_SDMMC_EXT_CON0, 1), MMC(SCLK_SDMMC_EXT_SAMPLE, "sdmmc_ext_sample", "clk_sdmmc_ext", - RK3328_SDMMC_EXT_CON1, 0), + RK3328_SDMMC_EXT_CON1, 1), }; static const char *const rk3328_critical_clocks[] __initconst = {
This reverts commit 82f4b67f018c88a7cc9337f0067ed3d6ec352648. According to a subsequent revert in the vendor kernel, the original change was based on unclear documentation and was in fact incorrect. Emprically, my board's HS200 eMMC at 200MHZ apparently gets lucky with a phase where this had no impact, but limiting max-frequency to 150MHz to match the nominal capability of the I/O pins made it virtually unusable, constantly throwing errors and retuning. With this revert, it starts behaving perfectly at 150MHz too. Fixes: 82f4b67f018c ("clk: rockchip: fix wrong mmc sample phase shift for rk3328") Signed-off-by: Robin Murphy <robin.murphy@arm.com> --- Resending with the edited commit log I actually meant, rather than the earlier draft I managed to generate the previuous patch from, since that one seems to have slipped through the cracks anyway. ybetter commit message drivers/clk/rockchip/clk-rk3328.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)