From patchwork Wed May 31 13:41:53 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 9757137 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 5248060360 for ; Wed, 31 May 2017 13:51:55 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4617E283C4 for ; Wed, 31 May 2017 13:51:55 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3AD88283FF; Wed, 31 May 2017 13:51:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id EF26C283C4 for ; Wed, 31 May 2017 13:51:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=CwBkbFrlQSB99QRzwjX6vinDOjt2vMOgr52I+c+AO6I=; b=D7j6iFg/Fa+JGkkxqLo8GYQlrX 6fcIIpWKbzTwOsNZ8cCwwkDGA/YeS+iEDaEu7toTUk6Vie8lcbyFIfLlgeWDywXDznCpOmz7zBRlT 6cSh4jFZmOphAmEGoleg13w4+/2lvYN2/ROPlJIBgNC5JY7Kr+mYccUhYq7ZJm7SRJRmNGVhelisx Ky35wc4y++9xXbcgyF7RMQVMW/9famexOZ+2l3wWo3708oEH2+RnbisyM7b1kpbYbQg/LLrLZIhQM zYBtt20TfbabZWjOBybN31QzOv8RQP59IDuVL3zePKjHLLXvW52/s/qifm592Nx1uHwtOz46mmbQh QATrutGw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1dG42O-0004Iv-Ur; Wed, 31 May 2017 13:51:48 +0000 Received: from mail.free-electrons.com ([62.4.15.54]) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1dG3te-00067k-LI for linux-arm-kernel@lists.infradead.org; Wed, 31 May 2017 13:42:51 +0000 Received: by mail.free-electrons.com (Postfix, from userid 110) id 460BE20F1B; Wed, 31 May 2017 15:42:04 +0200 (CEST) Received: from localhost (83.146.29.93.rev.sfr.net [93.29.146.83]) by mail.free-electrons.com (Postfix) with ESMTPSA id 1982B20E96; Wed, 31 May 2017 15:42:04 +0200 (CEST) From: Gregory CLEMENT To: Stephen Boyd , Mike Turquette , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 09/11] clk: mvebu: cp110: add sdio clock to cp-110 system controller Date: Wed, 31 May 2017 15:41:53 +0200 Message-Id: X-Mailer: git-send-email 2.11.0 In-Reply-To: References: In-Reply-To: References: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170531_064247_050123_F739E86A X-CRM114-Status: GOOD ( 15.92 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Petazzoni , Andrew Lunn , Jason Cooper , devicetree@vger.kernel.org, Omri Itach , Nadav Haklai , Kostya Porotchkin , Rob Herring , Neta Zur Hershkovits , Gregory CLEMENT , Shadi Ammouri , Marcin Wojtas , linux-arm-kernel@lists.infradead.org, Sebastian Hesselbarth MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Konstantin Porotchkin This commit updates the CP110 system controller driver to add the definition for a missing clock. The SDIO clock is dedicated driving the SDHCI interface and its frequency is 400MHz (2/5 of PLL source clock). The SDIO interface should be bound to this clock and not the core clock as in the older code. Using the wrong clock lead to a maximum SDHCI frequency of 250 Mhz, while the HW really supports up to 400 Mhz. This patch also fixes the NAND clock relationship documentation. Signed-off-by: Konstantin Porotchkin [gregory.clement@free-electrons.com: - use sdio instead of emmc to name the clock] Reviewed-by: Thomas Petazzoni Acked-by: Rob Herring Signed-off-by: Gregory CLEMENT --- drivers/clk/mvebu/cp110-system-controller.c | 28 ++++++++++++++++++---- 1 file changed, 23 insertions(+), 5 deletions(-) diff --git a/drivers/clk/mvebu/cp110-system-controller.c b/drivers/clk/mvebu/cp110-system-controller.c index ecbcae321424..8be7ae25c7eb 100644 --- a/drivers/clk/mvebu/cp110-system-controller.c +++ b/drivers/clk/mvebu/cp110-system-controller.c @@ -11,15 +11,16 @@ */ /* - * CP110 has 5 core clocks: + * CP110 has 6 core clocks: * * - APLL (1 Ghz) * - PPv2 core (1/3 APLL) * - EIP (1/2 APLL) - * - Core (1/2 EIP) + * - Core (1/2 EIP) + * - SDIO (2/5 APLL) * * - NAND clock, which is either: - * - Equal to the core clock + * - Equal to SDIO clock * - 2/5 APLL * * CP110 has 32 gatable clocks, for the various peripherals in the @@ -46,7 +47,7 @@ enum { CP110_CLK_TYPE_GATABLE, }; -#define CP110_MAX_CORE_CLOCKS 5 +#define CP110_MAX_CORE_CLOCKS 6 #define CP110_MAX_GATABLE_CLOCKS 32 #define CP110_CLK_NUM \ @@ -57,6 +58,7 @@ enum { #define CP110_CORE_EIP 2 #define CP110_CORE_CORE 3 #define CP110_CORE_NAND 4 +#define CP110_CORE_SDIO 5 /* A number of gatable clocks need special handling */ #define CP110_GATE_AUDIO 0 @@ -235,7 +237,8 @@ static int cp110_syscon_common_probe(struct platform_device *pdev, struct regmap *regmap; struct device *dev = &pdev->dev; struct device_node *np = dev->of_node; - const char *ppv2_name, *apll_name, *core_name, *eip_name, *nand_name; + const char *ppv2_name, *apll_name, *core_name, *eip_name, *nand_name, + *sdio_name; struct clk_hw_onecell_data *cp110_clk_data; struct clk_hw *hw, **cp110_clks; u32 nand_clk_ctrl; @@ -315,6 +318,17 @@ static int cp110_syscon_common_probe(struct platform_device *pdev, cp110_clks[CP110_CORE_NAND] = hw; + /* SDIO clock is APLL/2.5 */ + sdio_name = cp110_unique_name(dev, syscon_node, "sdio-core"); + hw = clk_hw_register_fixed_factor(NULL, sdio_name, + apll_name, 0, 2, 5); + if (IS_ERR(hw)) { + ret = PTR_ERR(hw); + goto fail_sdio; + } + + cp110_clks[CP110_CORE_SDIO] = hw; + /* create the unique name for all the gate clocks */ for (i = 0; i < ARRAY_SIZE(gate_base_names); i++) gate_name[i] = cp110_unique_name(dev, syscon_node, @@ -344,6 +358,8 @@ static int cp110_syscon_common_probe(struct platform_device *pdev, parent = ppv2_name; break; case CP110_GATE_SDIO: + parent = sdio_name; + break; case CP110_GATE_GOP_DP: parent = gate_name[CP110_GATE_GOP]; break; @@ -391,6 +407,8 @@ static int cp110_syscon_common_probe(struct platform_device *pdev, cp110_unregister_gate(hw); } + clk_hw_unregister_fixed_factor(cp110_clks[CP110_CORE_SDIO]); +fail_sdio: clk_hw_unregister_fixed_factor(cp110_clks[CP110_CORE_NAND]); fail_nand: clk_hw_unregister_fixed_factor(cp110_clks[CP110_CORE_CORE]);